Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for generating a properbroadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.
上傳時間： 2013-10-25
上傳用戶：banyou
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
上傳時間： 2013-11-12
上傳用戶：pans0ul
Abstract: Investment in smart meters and smart grid end equipment continues to grow worldwide as countriestry to make their electric delivery systems more efficient. However, as critical as the electric deliveryinfrastructure is, it is normally not secured and thus subject to attack. This article describes the concept oflife-cycle security—the idea that embedded equipment in the smart grid must have security designed into theentire life of the product, even back to the contract manufacturer. We also talk about how life-cycle securityapplies to embedded equipment in the smart grid. Potential threats are discussed, as are potential solutionsto mitigate the risks posed by those threats.
上傳時間： 2014-12-24
上傳用戶：熊少鋒
高的工作電壓高達100V N雙N溝道MOSFET同步驅動 The D810DCDC is a synchronous step-down switching regulator controller that can directly step-down voltages from up to 100V, making it ideal for telecom and automotive applications. The D810DCDC uses a constant on-time valley current control architecture to deliver very low duty cycles with accurate cycle-by-cycle current limit, without requiring a sense resistor. A precise internal reference provides 0.5% DC accuracy. A high bandwidth (25MHz) error amplifi er provides very fast line and load transient response. Large 1Ω gate drivers allow the D810DCDC to drive multiple MOSFETs for higher current applications. The operating frequency is selected by an external resistor and is compensated for variations in VIN and can also be synchronized to an external clock for switching-noise sensitive applications. Integrated bias control generates gate drive power from the input supply during start-up and when an output shortcircuit occurs, with the addition of a small external SOT23 MOSFET. When in regulation, power is derived from the output for higher effi ciency.
上傳時間： 2013-10-24
上傳用戶：wd450412225
Although recent popular attention is focused on LithiumIon batteries, one must not forget that other batterychemistries, such as Nickel Cadmium (NiCd) and NickelMetal Hydride (NiMH) have advantages in rechargeablepower systems. Nickel-based batteries are robust, capableof high discharge rates, have good cycle life, do notrequire special protection circuitry and are less expensivethan Li-Ion. Among the two, NiMH batteries are rapidlyreplacing NiCd because of their higher capacity (40% to50% more) and the environmental concerns of the toxiccadmium contained in NiCd batteries.
上傳時間： 2013-11-04
上傳用戶：qq10538412
IC 特色 : ˙ 半諧振模式之 ZVS零電壓切換 , 能有效降低切換損失 , 提高效率 , 并具展頻功能 , 改善EMI . ˙ 輕 / 重載的 Duty Factor 皆在 CCM 與 DCM 邊緣 , 是最能發揮次級 "同步整流" 效率的一種工作模式 . ˙ 空載時進入 Cycle Skipping ( Typical 0.3W ) , 有效達成環保規範 . ˙ 內建 "LEB前緣遮沒" 功能 , 避免電流迴授失真 . ˙ 能隨輸入電壓變化 , 自動補償 OPP過功率保護點 . ˙ 精密的 OVP 過壓保護點可自行設定 . ˙ 完整的保護功能 : OVP過壓保護 , OCP過流保護 , OPP過載保護 , SWP線圈短路保護 , SCP輸出短路保護 , OTP過溫度保護 .
上傳時間： 2014-12-24
上傳用戶：回電話#
實時時鐘是微機保護裝置的重要部件，在討論PCF8583結構與功能的基礎上，提出采用dsPIC33F系列微處理器與串行I2C時鐘PCF8583的接口設計方案，給出了相應的接口電路與軟件流程。該設計方案結構簡單，可靠性高，開發周期短，具有一定的實用與參考價值。所設計的微機保護裝置已投入現場運行，效果良好。 Abstract: Real-time clock chip is an important part in microcomputer protection device.Based on discussing the structure and function of PCF8583，a new interface scheme which uses dsPIC33F microprocessor and serial clock chip（I2C）PCF8583is proposed.The method of the circuit design and the main software flow are introduced in this paper.The scheme has simple structure，higher reliability and shorter exploitation cycle，so has definite practicality or reference value.The microcomputer protection device has been put into operation with better effects.
上傳時間： 2013-11-18
上傳用戶：Thuan
數字信號處理器dsPIC33F集多通道高精度A/D轉換、多通訊模式、看門狗、CMOS Flash技術等于一體，其內部可完成所有數據操作，實現總線不出芯片技術。將該處理器應用于微機保護裝置，提出基于dsPIC33F微處理器的微機保護裝置的設計方案，給出相應的接口電路與軟件流程。該設計方案結構簡單，性價比及可靠性高，開發周期短，具有一定的實用推廣價值。所研制的微機保護裝置現場運行效果良好。 Abstract: The dsPIC33F microprocessor has a plentiful interior resource which contains multi-channel，high precision A/D converters，multi-communication module，watchdog，CMOS Flash technology，and so on.All data manipulations is accomplished interiorly.What is more，it makes the technology that bus does not go beyond the chip comes into practice.The paper put forwards a design scheme based on dsPIC33F microprocessor.The scheme has the advantages of simple structure，high reliability and shortened exploitation cycle.What is more，it has definite practicality and reference.The microcomputer protection device has been put into operation with excellent effects.
上傳時間： 2013-11-16
上傳用戶：開懷常笑
介紹了用單片機C 語言實現無功補償中電容組循環投切的基本原理和算法，并舉例說明。關鍵詞：循環投切;C51;無功補償中圖分類號： TM76 文獻標識碼： BAbstract: This paper introduces the aplication of C51 in the controlling of capacitorsuits cycle powered to be on and off in reactive compensation.it illustrate thefondamental principle and algorithm with example.Key words: cycle powered to be on and off; C51; reactive compensation 為提高功率因數，往往采用補償電容的方法來實現。而電容器的容量是由實時功率因數與標準值進行比較來決定的，實時功率因數小于標準值時，需投入電容組，實時功率因數大于標準值時，則需切除電容組。投切方式的不合理，會對電容器造成損壞，現有的控制器多采用“順序投切”方式，在這種投切方式下排序在前的電容器組，先投后切；而后面的卻后投先切。這不僅使處于前面的電容組經常處于運行狀態，積累熱量不易散失，影響其使用壽命，而且使后面的投切開關經常動作，同樣減少壽命。合理的投切方式應為“循環投切”。這種投切方式使先投入的運行的電容組先退出，后投的后切除，從而使各組電容及投切開關使用機率均等，降低了電容組的平均運行溫度，減少了投切開關的動作次數，延長了其使用壽命。
上傳時間： 2014-12-27
上傳用戶：hopy
The CAT28LV64 is a low voltage, low power, CMOS Parallel EEPROM organized as 8K x 8−bits. It requires a simple interface for in−system programming. On−chip address and data latches, self−timed write cycle with auto−clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bit signal the start and end of the self−timed write cycle. Additionally, the CAT28LV64 features hardware and software write protection.
上傳時間： 2013-11-16
上傳用戶：浩子GG
