Spartan-3AN 器件帶有可以用于儲(chǔ)存配置數(shù)據(jù)的片上Flash 存儲(chǔ)器。如果在您的設(shè)計(jì)中Flash 存儲(chǔ)器沒(méi)有與外部相連，那么Flash 存儲(chǔ)器無(wú)法從I/O 引腳讀取數(shù)據(jù)。由于Flash 存儲(chǔ)器在FPGA 內(nèi)部，因此配置過(guò)程中Spartan-3AN 器件比特流處于隱藏狀態(tài)。這一配置成了設(shè)計(jì)安全的起點(diǎn)，因?yàn)闊o(wú)法直接從Flash 存儲(chǔ)器拷貝設(shè)計(jì)。
上傳時(shí)間： 2013-10-31
上傳用戶：R50974
The introduction of Spartan-3™ devices has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the “almostfreestage.” With these new FPGAs falling under $20, involume, with over 1 million system gates, and under $5for 100K gate-level units, any design with programmablelogic has a readily available 8- or 16-bit processor costingless than 75 cents and 32-bit processor for less than $1.50.
上傳時(shí)間： 2013-10-21
上傳用戶：ligi201200
This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can be expanded by the user to perform additional operations usingthe remaining CPLD resources
標(biāo)簽： CoolRunner-II Xilinx XAPP CPLD
上傳時(shí)間： 2013-12-16
上傳用戶：qwer0574
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.
標(biāo)簽： Spartan XAPP 1065 FPGA
上傳時(shí)間： 2013-11-01
上傳用戶：hjkhjk
本白皮書(shū)主要介紹 Spartan®-6 FPGA 如何滿足大批量系統(tǒng)的需求。包括經(jīng)濟(jì)高效地驅(qū)動(dòng)商用存儲(chǔ)器芯片、構(gòu)建芯片間的高性能接口、創(chuàng)新型節(jié)電模式，這些只是高性能、低功耗、低成本 Spartan-6 FPGA 解決諸多問(wèn)題的一部分。
上傳時(shí)間： 2015-01-02
上傳用戶：jx_wwq
WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮點(diǎn)DSP算法實(shí)現(xiàn)方案： High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
上傳時(shí)間： 2013-10-21
上傳用戶：huql11633
Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
上傳時(shí)間： 2013-12-07
上傳用戶：bruce
一些應(yīng)用利用 Xilinx FPGA 在每次啟動(dòng)時(shí)可改變配置的能力，根據(jù)所需來(lái)改變 FPGA 的功能。Xilinx Platform Flash XCFxxP PROM 的設(shè)計(jì)修訂 (Design Revisioning) 功能，允許用戶在單個(gè)PROM 中將多種配置存儲(chǔ)為不同的修訂版本，從而簡(jiǎn)化了 FPGA 配置更改。在 FPGA 內(nèi)部加入少量的邏輯，用戶就能在 PROM 中存儲(chǔ)的多達(dá)四個(gè)不同的修訂版本之間進(jìn)行動(dòng)態(tài)切換。多重啟動(dòng)或從多個(gè)設(shè)計(jì)修訂進(jìn)行動(dòng)態(tài)重新配置的能力，與 Spartan™-3E FPGA 和第三方并行 flashPROM 一起使用時(shí)所提供的 MultiBoot 選項(xiàng)相似。本應(yīng)用指南將進(jìn)一步說(shuō)明 Platform Flash PROM 如何提供附加選項(xiàng)來(lái)增強(qiáng)配置失敗時(shí)的安全性，以及如何減少引腳數(shù)量和板面積。此外，Platform Flash PROM 還為用戶提供其他優(yōu)勢(shì)：iMPACT 編程支持、單一供應(yīng)商解決方案、低成本板設(shè)計(jì)和更快速的配置加載。本應(yīng)用指南還詳細(xì)地介紹了一個(gè)包含 VHDL 源代碼的參考設(shè)計(jì)。
標(biāo)簽： Platform Flash XAPP PROM
上傳時(shí)間： 2013-10-10
上傳用戶：wangcehnglin
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
標(biāo)簽： xilinx Zynq 7000 EPP
上傳時(shí)間： 2013-10-09
上傳用戶：evil
Xilinx 高性能 CPLD、FPGA 和配置 PROM 系列具備在系統(tǒng)可編程性、可靠的引腳鎖定以及JTAG 邊界掃描測(cè)試功能。此強(qiáng)大的功能組合允許設(shè)計(jì)人員在進(jìn)行重大更改時(shí)，仍能保留原始的器件引腳，從而避免重組 PC 板。通過(guò)利用嵌入式控制器從板載 RAM 或 EPROM 對(duì)這些CPLD 和 FPGA 編程，設(shè)計(jì)人員可輕松升級(jí)、修改和測(cè)試設(shè)計(jì)，即使在現(xiàn)場(chǎng)也是如此。
上傳時(shí)間： 2013-11-03
上傳用戶：dongbaobao
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