國(guó)際會(huì)議上關(guān)于磨損平衡的一片論文：A Stackable Wear-Leveling Module for Linux-Based Flash File Systems
標(biāo)簽： Wear-Leveling Linux-Based Stackable Systems
上傳時(shí)間： 2014-08-15
上傳用戶：Pzj
是PDF文檔，是臺(tái)灣一大學(xué)教授的論文，主要是講NAND FLASH Wear leveling 算法的理論性文章，上傳上來(lái)是提供大家一起學(xué)習(xí)！
標(biāo)簽： 文檔
上傳時(shí)間： 2016-10-13
上傳用戶：evil
一． eMMC的概述eMMC (Embedded MultiMedia Card) 為MMC協(xié)會(huì)所訂立的內(nèi)嵌式存儲(chǔ)器標(biāo)準(zhǔn)規(guī)格，主要是針對(duì)手機(jī)產(chǎn)品為主。eMMC的一個(gè)明顯優(yōu)勢(shì)是在封裝中集成了一個(gè)控制器， 它提供標(biāo)準(zhǔn)接口并管理閃存， 使得手機(jī)廠商就能專注于產(chǎn)品開(kāi)發(fā)的其它部分，并縮短向市場(chǎng)推出產(chǎn)品的時(shí)間。這些特點(diǎn)對(duì)于希望通過(guò)縮小光刻尺寸和降低成本的NAND供應(yīng)商來(lái)說(shuō)，具有同樣的重要性。二． eMMC的優(yōu)點(diǎn)eMMC目前是最當(dāng)紅的移動(dòng)設(shè)備本地存儲(chǔ)解決方案，目的在于簡(jiǎn)化手機(jī)存儲(chǔ)器的設(shè)計(jì)，由于NAND Flash 芯片的不同廠牌包括三星、KingMax、東芝(Toshiba) 或海力士(Hynix) 、美光(Micron) 等，入時(shí)，都需要根據(jù)每家公司的產(chǎn)品和技術(shù)特性來(lái)重新設(shè)計(jì)，過(guò)去并沒(méi)有哪個(gè)技術(shù)能夠通用所有廠牌的NAND Flash 芯片。而每次NAND Flash 制程技術(shù)改朝換代，包括70 納米演進(jìn)至50 納米，再演進(jìn)至40 納米或30 納米制程技術(shù)，手機(jī)客戶也都要重新設(shè)計(jì)， 但半導(dǎo)體產(chǎn)品每1 年制程技術(shù)都會(huì)推陳出新， 存儲(chǔ)器問(wèn)題也拖累手機(jī)新機(jī)種推出的速度，因此像eMMC這種把所有存儲(chǔ)器和管理NAND Flash 的控制芯片都包在1 顆MCP上的概念，逐漸風(fēng)行起來(lái)。eMMC的設(shè)計(jì)概念，就是為了簡(jiǎn)化手機(jī)內(nèi)存儲(chǔ)器的使用，將NAND Flash 芯片和控制芯片設(shè)計(jì)成1 顆MCP芯片，手機(jī)客戶只需要采購(gòu)eMMC芯片，放進(jìn)新手機(jī)中，不需處理其它繁復(fù)的NAND Flash 兼容性和管理問(wèn)題，最大優(yōu)點(diǎn)是縮短新產(chǎn)品的上市周期和研發(fā)成本，加速產(chǎn)品的推陳出新速度。閃存Flash 的制程和技術(shù)變化很快，特別是TLC 技術(shù)和制程下降到20nm階段后，對(duì)Flash 的管理是個(gè)巨大挑戰(zhàn)，使用eMMC產(chǎn)品，主芯片廠商和客戶就無(wú)需關(guān)注Flash 內(nèi)部的制成和產(chǎn)品變化，只要通過(guò)eMMC的標(biāo)準(zhǔn)接口來(lái)管理閃存就可以了。這樣可以大大的降低產(chǎn)品開(kāi)發(fā)的難度和加快產(chǎn)品上市時(shí)間。eMMC可以很好的解決對(duì)MLC 和TLC 的管理， ECC 除錯(cuò)機(jī)制(Error Correcting Code) 、區(qū)塊管理(BlockManagement)、平均抹寫(xiě)儲(chǔ)存區(qū)塊技術(shù) (Wear Leveling) 、區(qū)塊管理（ Command Managemen）t，低功耗管理等。eMMC核心優(yōu)點(diǎn)在于生產(chǎn)廠商可節(jié)省許多管理NAND Flash 芯片的時(shí)間，不必關(guān)心NAND Flash 芯片的制程技術(shù)演變和產(chǎn)品更新?lián)Q代，也不必考慮到底是采用哪家的NAND Flash 閃存芯片，如此， eMMC可以加速產(chǎn)品上市的時(shí)間，保證產(chǎn)品的穩(wěn)定性和一致性。
標(biāo)簽： emmc
上傳時(shí)間： 2022-06-20
上傳用戶：jiabin
hard wear...............
上傳時(shí)間： 2013-12-23
上傳用戶：er1219
對(duì)于瀝青混凝土攤鋪機(jī)自動(dòng)找平控制系統(tǒng)來(lái)說(shuō)，數(shù)字式控制系統(tǒng)的研制是目前的一個(gè)方向。介紹了一種基于CAN總線的數(shù)字式自動(dòng)找平控制系統(tǒng)。該系統(tǒng)以CAN總線作為通信方式，PWM控制信號(hào)通過(guò)C8051F040單片機(jī)內(nèi)部PCA可編程計(jì)數(shù)器陣列產(chǎn)生，并具有結(jié)構(gòu)簡(jiǎn)單、信號(hào)穩(wěn)定、實(shí)時(shí)性強(qiáng)、易擴(kuò)展的特點(diǎn)。通過(guò)硬件實(shí)現(xiàn)和系統(tǒng)運(yùn)行達(dá)到了比較理想的控制效果，驗(yàn)證了系統(tǒng)的可行性。 Abstract: A digital auto-leveling control system based on CAN Bus is introduced.It uses CAN Bus as the method of communication and creates PWM signals by programmable counter array in C8051F040 microcontroller. The system is simple, stable, real-time and expansive.
標(biāo)簽： CAN 總線 數(shù)字式 控制系統(tǒng)設(shè)計(jì)
上傳時(shí)間： 2013-10-09
上傳用戶：ligi201200
Because of the poor observability of Inertial Navigation System on stationary base, the estimation error of the azimuth will converge very slowly in initial alignment by means of Kalmari filtering, and making the time initial alignment is longer. In this paper, a fast estimation method of the azimuth error is creatively proposed for the initial alignment of INS on stationary base. On the basis of the the fast convergence of the leveling error, the azimuth error can be directly calculated. By means of this fast initial alignment method, the time of initial alignment is reduced greatly. The computer simulation results illustrate the efficiency of the method.
標(biāo)簽： observability Navigation estimation stationary
上傳時(shí)間： 2014-01-03
上傳用戶：wuyuying
Evaluation of friction mechanisms and wear rates on rubber tire materials by low-cost laboratory tests
上傳時(shí)間： 2016-05-16
上傳用戶：zz17110439
Battery systems for energy storage are among the most relevant technologies of the 21 st century. They – in particular modern lithium-ion batteries (LIB) – are enablers for the market success of electric vehicles (EV) as well as for stationary energy storage solutions for balancing fluctuations in electricity grids resulting from the integrationofrenewableenergysourceswithvolatilesupply 1 .BothEVandstationary storage solutions are important because they foster the transition from the usage of fossil energy carriers towards cleaner renewable energy sources. Furthermore, EV cause less local air pollution and noise emissions compared to conventional combustion engine vehicles resulting in better air quality especially in urban areas. Unfortunately, to this day, various technological and economic challenges impede a broad application of batteries for EV as well as for large scale energy storage and load leveling in electricity grids.
標(biāo)簽： Multiscale Simulation Approach
上傳時(shí)間： 2020-06-07
上傳用戶：shancjb
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
標(biāo)簽： DDR4
上傳時(shí)間： 2022-01-09
上傳用戶：
3.DDR布線細(xì)節(jié)i.MX6DDR的布線，可以將所有信號(hào)分成3組：數(shù)據(jù)線組、地址線組和控制線組，每組各自設(shè)置自己的布線規(guī)則，但同時(shí)也要考慮組與組之間的規(guī)則。3.1數(shù)據(jù)線的交換在DDR3的布線中，可以根據(jù)實(shí)際情況交換數(shù)據(jù)線的線序，但必須保證是以字節(jié)為單位（數(shù)據(jù)0~7間是允許交換線序，跨字節(jié)是不允許的），這樣可以簡(jiǎn)化設(shè)計(jì)。■布線盡量簡(jiǎn)短，減少過(guò)孔數(shù)量。■布線時(shí)避免改變走線參考層面。■數(shù)據(jù)線線序，推薦DO、D8、D16、D24、D32、D40、D48、D56不要改變，其它的數(shù)據(jù)線可以在字節(jié)內(nèi)自由調(diào)換（see the“Write Leveling"sectioninJESD79-3E■DQS和DQM不能調(diào)換，必須在相應(yīng)通道。3.2DDR3（64bits）T型拓?fù)浣榻B當(dāng)設(shè)計(jì)采用T型拓?fù)浣Y(jié)構(gòu)，請(qǐng)確認(rèn)以下信息。■布線規(guī)則見(jiàn)上文表2。■終端電阻可以省略。■布線長(zhǎng)度的控制。DDR數(shù)量限制在4片以下。
標(biāo)簽： ddr3
上傳時(shí)間： 2022-07-05
上傳用戶：
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
