This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VhDl) design engineers and is offered as guidance for the development of VhDl modelswhich are compliant with the VhDl Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VhDl modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VhDl
上傳時間： 2013-11-20
上傳用戶：pzw421125
本文詳細(xì)討論了VhDl語句對PLD設(shè)計的影響和設(shè)計經(jīng)驗(yàn)，經(jīng)典文章，值得仔細(xì)閱讀消化。,PLD Programming Using VhDl
標(biāo)簽： Programming Using VhDl PLD
上傳時間： 2013-10-14
上傳用戶：www240697738
本文簡單討論并總結(jié)了VhDl、Verilog，System verilog 這三中語言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標(biāo)簽： Verilog verilog System VhDl
上傳時間： 2014-03-03
上傳用戶：zhtzht
利用一塊芯片完成除時鐘源、按鍵、揚(yáng)聲器和顯示器（數(shù)碼管）之外的所有數(shù)字電路功能。所有數(shù)字邏輯功能都在CPLD器件上用VhDl語言實(shí)現(xiàn)。這樣設(shè)計具有體積小、設(shè)計周期短（設(shè)計過程中即可實(shí)現(xiàn)時序仿真）、調(diào)試方便、故障率低、修改升級容易等特點(diǎn)。 本設(shè)計采用自頂向下、混合輸入方式（原理圖輸入—頂層文件連接和VhDl語言輸入—各模塊程序設(shè)計）實(shí)現(xiàn)數(shù)字鐘的設(shè)計、下載和調(diào)試。
標(biāo)簽： CPLD VhDl 語言 數(shù)字
上傳時間： 2013-10-24
上傳用戶：古谷仁美
ZBT SRAM控制器參考設(shè)計,xilinx提供VhDl代碼 Description: Contains the following files readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform: All Installation/Use: Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.
標(biāo)簽： xilinx SRAM VhDl ZBT
上傳時間： 2013-10-25
上傳用戶：peterli123456
USB接口控制器參考設(shè)計,xilinx提供VhDl代碼 usb xilinx VhDl ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 2 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
上傳時間： 2013-10-29
上傳用戶：zhouchang199
ref-sdr-sdram-VhDl代碼 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上傳時間： 2013-10-23
上傳用戶：半熟1994
UART 4 UART參考設(shè)計，Xilinx提供VhDl代碼 uart_VhDl This zip file contains the following folders: \VhDl_source -- Source VhDl files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \VhDl_testfixture -- VhDl Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VhDl file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
標(biāo)簽： UART Xilinx VhDl 參考設(shè)計
上傳時間： 2013-11-02
上傳用戶：18862121743
各種功能的計數(shù)器實(shí)例（VhDl源代碼）:
上傳時間： 2013-10-19
上傳用戶：xanxuan
各種功能的計數(shù)器實(shí)例（VhDl源代碼）:ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; ld : IN BIT; enable : IN BIT; up_down : IN BIT; qa : OUT INTEGER RANGE 0 TO 255; qb : OUT INTEGER RANGE 0 TO 255; qc : OUT INTEGER RANGE 0 TO 255; qd : OUT INTEGER RANGE 0 TO 255; qe : OUT INTEGER RANGE 0 TO 255; qf : OUT INTEGER RANGE 0 TO 255; qg : OUT INTEGER RANGE 0 TO 255; qh : OUT INTEGER RANGE 0 TO 255; qi : OUT INTEGER RANGE 0 TO 255;
上傳時間： 2013-10-09
上傳用戶：松毓336
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