Cypress - EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller
標(biāo)簽： Microcontroller Controller High-Speed Peripheral
上傳時(shí)間： 2017-08-15
上傳用戶：ippler8
Supplemental information for a high-speed serial bus that integrates well with most IEEE standard 32-bit and 64-bit parallel buses is specified. It is intended to extend the usefulness of a low-cost interconnect between external peripherals, IEEE Std 1394-1995. This standard follows the ISO/IEC 13213:1994 Command and Status Register (CSR) architecture.
標(biāo)簽： Supplemental information high-speed integrates
上傳時(shí)間： 2014-03-07
上傳用戶：jjj0202
HIGH SPeed serdes designs and connectors and simulation models simulations used in signal Integrity and also has practical evaluation aof all connectors
上傳時(shí)間： 2015-04-09
上傳用戶：1234wei
JPEG2000是由ISO/ITU-T組織下的IEC JTC1/SC29/WG1小組制定的下一代靜止圖像壓縮標(biāo)準(zhǔn).與JPEG(Joint Photographic Experts Group)相比,JPEG2000能夠提供更好的數(shù)據(jù)壓縮比,并且提供了一些JPEG所不具有的功能[1].JPEG2000具有的多種特性使得它具有廣泛的應(yīng)用前景.但是,JPEG2000是一個(gè)復(fù)雜編碼系統(tǒng),目前為止的軟件實(shí)現(xiàn)方案的執(zhí)行時(shí)間和所需的存儲量較大,若想將JPEG2000應(yīng)用于實(shí)際中,有著較大的困難,而用硬件電路實(shí)現(xiàn)JPEG2000或者其中的某些模塊,必然能夠減少JPEG200的執(zhí)行時(shí)間,因而具有重要的意義.本文首先簡單介紹了JPEG2000這一新的靜止圖像壓縮標(biāo)準(zhǔn),然后對算術(shù)編碼的原理及實(shí)現(xiàn)算法進(jìn)行了深入的研究,并重點(diǎn)探討了JPEG2000中算術(shù)編碼的硬件實(shí)現(xiàn)問題,給出了一種硬件最優(yōu)化的算術(shù)編碼實(shí)現(xiàn)方案.最后使用硬件描述語言(Very High Speed Integrated Circuit Hardware Description Language,VHDL)在寄存器傳輸級(Register Transfer Level,RTL描述了該硬件最優(yōu)化的算術(shù)編碼實(shí)現(xiàn)方案,并以Altera 20K200E FPGA為基礎(chǔ),在Active-HDL環(huán)境中進(jìn)行了功能仿真,在Quartus Ⅱ集成開發(fā)環(huán)境下完成了綜合以及后仿真,綜合得到的最高工作時(shí)鐘頻率達(dá)45.81MHz.在相同的輸入條件下,輸出結(jié)果表明,本文設(shè)計(jì)的硬件算術(shù)編碼器與實(shí)現(xiàn)JPEG2000的軟件:Jasper[2]中的算術(shù)編碼模塊相比,處理時(shí)間縮短了30﹪左右.因而本文的研究對于JPEG2000應(yīng)用于數(shù)字監(jiān)控系統(tǒng)等實(shí)際應(yīng)用有著重要的意義.
標(biāo)簽： JPEG 2000 FPGA 算術(shù)編碼
上傳時(shí)間： 2013-05-16
上傳用戶：671145514
數(shù)字射頻存儲器(Digital Radio FreqlJencyr：Memory DRFM)具有對射頻信號和微波信號的存儲、處理及傳輸能力，已成為現(xiàn)代雷達(dá)系統(tǒng)的重要部件。現(xiàn)代雷達(dá)普遍采用了諸如脈沖壓縮、相位編碼等更為復(fù)雜的信號處理技術(shù)，DRFM由于具有處理這些相干波形的能力，被越來越廣泛地應(yīng)用于電子對抗領(lǐng)域作為射頻頻率源。目前，國內(nèi)外對DRFM技術(shù)的研究還處于起步階段，DRFM部件在采樣率、采樣精度及存儲容量等方面，還不能滿足現(xiàn)代雷達(dá)信號處理的要求。 本文介紹了DRFM的量化類型、基本組成及其工作原理，在現(xiàn)有的研究基礎(chǔ)上提出了一種便于工程實(shí)現(xiàn)的設(shè)計(jì)方法，給出了基于現(xiàn)場可編程門陣列(Field Programmable Gate Array FPGA)實(shí)現(xiàn)的幅度量化DRFM設(shè)計(jì)方案。本方案的采樣率為1 GHz、采樣精度12位，具體實(shí)現(xiàn)是采用4個(gè)采樣率為250 MHz的ADC并行交替等效時(shí)間采樣以達(dá)到1 GHz的采樣率。單通道內(nèi)采用數(shù)字正交采樣技術(shù)進(jìn)行相干檢波，用于保存信號復(fù)包絡(luò)的所有信息。利用FPGA器件實(shí)現(xiàn)DRFM的控制器和多路采樣數(shù)據(jù)緩沖器，采用硬件描述語言(Very High Speed}lardware Description Language VHDL)實(shí)現(xiàn)了DRFM電路的FPGA設(shè)計(jì)和功能仿真、時(shí)序分析。方案中采用了大量的低壓差分信號(Low Voltage Differential Signaling LVDS)邏輯的芯片，從而大大降低了系統(tǒng)的功耗，提高了系統(tǒng)工作的可靠性。本文最后對采用的數(shù)字信號處理算法進(jìn)行了仿真，仿真結(jié)果證明了設(shè)計(jì)方案的可行性。 本文提出的基于FPGA的多通道DRFM系統(tǒng)與基于專用FIFO存儲器的DRFM相比，具有更高的性能指標(biāo)和優(yōu)越性。
上傳時(shí)間： 2013-06-01
上傳用戶：lanwei
Recent advances in low voltage silicon germaniumand BiCMOS processes have allowed the design andproduction of very high speed amplifi ers. Because theprocesses are low voltage, most of the amplifi er designshave incorporated differential inputs and outputs to regainand maximize total output signal swing. Since many lowvoltageapplications are single-ended, the questions arise,“How can I use a differential I/O amplifi er in a single-endedapplication?” and “What are the implications of suchuse?” This Design Note addresses some of the practicalimplications and demonstrates specifi c single-endedapplications using the 3GHz gain-bandwidth LTC6406differential I/O amplifi er.
標(biāo)簽： 單端應(yīng)用 差分 放大器
上傳時(shí)間： 2013-11-23
上傳用戶：rocketrevenge
一種硬件描述語言（HDL），英文全稱為Very High Speed Integrated Circuit Hardware Description Language ，超高速集成電路硬件描述語言。
上傳時(shí)間： 2016-05-12
上傳用戶：waizhang
VHDL是由美國國防部為描述電子電路所開發(fā)的一種語言，其全稱為(Very High Speed Integrated Circuit) Hardware Description Language。 與另外一門硬件描述語言Verilog HDL相比，VHDL更善于描述高層的一些設(shè)計(jì)，包括系統(tǒng)級（算法、數(shù)據(jù)通路、控制）和行為級（寄存器傳輸級），而且VHDL具有設(shè)計(jì)重用、大型設(shè)計(jì)能力、可讀性強(qiáng)、易于編譯等優(yōu)點(diǎn)逐漸受到硬件設(shè)計(jì)者的青睞。但是，VHDL是一門語法相當(dāng)嚴(yán)格的語言，易學(xué)性差，特別是對于剛開始接觸VHDL的設(shè)計(jì)者而言，經(jīng)常會因某些小細(xì)節(jié)處理不當(dāng)導(dǎo)致綜合無法通過。為此本文就其中一些比較典型的問題展開探討，希望對初學(xué)者有所幫助，提高學(xué)習(xí)進(jìn)度。
上傳時(shí)間： 2017-02-18
上傳用戶：nanshan
The STi7200 is a new generation, high-definition set-top box/DVD decoder chip, and provides very high performance for low-cost HD systems. With enhanced performance over the STx7109, it includes both Windows Media Video 9 and H.264 video decoders for new, low bitrate applications. The STi7200 is able to decode two HD programs
標(biāo)簽： high-definition generation provides decoder
上傳時(shí)間： 2013-11-29
上傳用戶：xg262122
The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.
上傳時(shí)間： 2013-10-24
上傳用戶：s藍(lán)莓汁
蟲蟲下載站版權(quán)所有 京ICP備2021023401號-1
