This is GPS Matlab findPreambles finds the first preamble occurrence in the bit stream of each channel. The preamble is verified by check of the spacing between preambles [6sec] and parity checking of the first two words in a subframe. At the same time function returns list of channels, that are in tracking state and with VALID preambles in the nav data stream.
標簽： findPreambles occurrence the preamble
上傳時間： 2013-12-23
上傳用戶：秦莞爾w
Computation of loudness (Zwicker model) according to ISO 532B / DIN 45631 norms. This model is VALID for steady sounds. Code based on BASIC program published in the following article: Program for calculating loudness according to DIN 45 631 (ISO 532B)", E.Zwicker and H.Fastl, J.A.S.J (E) 12, 1 (1991).
上傳時間： 2016-11-14
上傳用戶：zztony16
The SP2526A device is a dual +3.0V to +5.5V USB Supervisory Power Control Switch ideal for self-powered and bus-powered Universal Serial Bus (USB) applications. Each switch has low on-resistance (110mΩ typical) and can supply 500mA minimum. The fault currents are limited to 1.0A typical and the flag output pin for each switch is available to indicate fault conditions to the USB controller. The thermal shutdown feature will prevent damage to the device when subjected to excessive current loads. The undervoltage lockout feature will ensure that the device will remain off unless there is a VALID input voltage present.
標簽： High-Side Switch Power Dual USB
上傳時間： 2019-03-06
上傳用戶：bhitr
軟件開發人員必備工具書，，目錄如下Welcome to Software Construction [1]1.1 What Is Software Construction?1.2 Why Is Software Construction Important?1.3 How to Read This Book......7.1 VALID Reasons to Create a Routine7.2 Design at the Routine Level7.3 Good Routine Names7.4 How Long Can a Routine Be?7.5 How to Use Routine Parameters7.6 Special Considerations in the Use of Functions7.7 Macro Routines and Inline RoutinesDefensive Programming [5.6 + new material]8.1 Protecting Your Program From InVALID Inputs8.2 Assertions8.3 Error Handling Techniques8.4 Exceptions8.5 Barricade Your Program to Contain the Damage Caused by Errors8.6 Debugging Aids8.7 Determining How Much Defensive Programming to Leave in Production Code8.8 Being Defensive About Defensive ProgrammingThe Pseudocode Programming Process [4+new material]9.1 Summary of Steps in Building Classes and Routines9.2 Pseudocode for Pros9.3 Constructing Routines Using the PPP9.4 Alternatives to the PPP......
上傳時間： 2021-12-08
上傳用戶：20125101110
FPGA讀取OV5640攝像頭數據并通過VGA或LCD屏顯示輸出的Verilog邏輯源碼Quartus工程文件+文檔說明，FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data VALID input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上傳時間： 2021-12-18
上傳用戶：
