·SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling ver
標簽： nbsp SystemVerilog Design for
上傳時間： 2013-07-14
上傳用戶：ainimao
在PC機上運行cadence需要先運行命令:source filename,此處filename指.cshrc,或其他具有該文件內容但名字不同的文件,該文件必須有set DISPLAY 本機IP:0.0 語句,同時應將其他雷同設置封住.可以先從工作站上下載.cshrc文件,然后用notepad修改顯示設置相,不可用其他編輯器,否則文本文件格式會不一樣.記住,必須將顯示器設置為256色.
上傳時間： 2013-09-05
上傳用戶：超凡大師
15.2 已經加入了有關貫孔及銲點的Z軸延遲計算功能. 先開啟 Setup - Constraints - Electrical constraint sets 下的 DRC 選項. 點選 Electrical Constraints dialog box 下 Options 頁面 勾選 Z-Axis delay欄.
上傳時間： 2013-10-08
上傳用戶：王慶才
Abstract: Alexander Graham Bell patented twisted pair wires in 1881. We still use them today because they work so well. In addition we have the advantage ofincredible computer power within our world. Circuit simulators and filter design programs are available for little or no cost. We combine the twisted pair and lowpassfilters to produce spectacular rejection of radio frequency interference (RFI) and electromagnetic interference (EMI). We also illustrate use of a precision resistorarray to produce a customizable differential amplifier. The precision resistors set the gain and common mode rejection ratios, while we choose the frequencyresponse.
上傳時間： 2014-11-26
上傳用戶：Vici
Abstract: Using a DAC and a microprocessor supervisor, the system safety can be improved in industrial controllers, programmablelogiccontrollers (PLC), and data-acquisition systems. The analog output is set to zero-scale (or pin-programmable midscale) when amicroprocessor failure, optocoupler failure, or undervoltage condition occurs. A simple application is shown on how to implement thisfunction.
上傳時間： 2013-10-17
上傳用戶：sjb555
This unique guide to designing digital VLSI circuits takes a top-down approach, reflecting the natureof the design process in industry. Starting with architecture design, the book explains the why andhow of digital design, using the physics that designers need to know, and no more.Covering system and component aspects, design verification, VHDL modelling, clocking, signalintegrity, layout, electricaloverstress, field-programmable logic, economic issues, and more, thescope of the book is singularly comprehensive.
標簽： Integrated Digital Circuit Design
上傳時間： 2013-11-04
上傳用戶：life840315
比例控制(P)是一種最簡單的控制方式。其控制器的輸出與輸入誤差信號成比例關系。根據設備有所不同，比例帶一般為2～10％(溫度控制)。但是，僅僅是P 控制的話，會產生下面將提到的off set (穩態誤差)，所以一般加上積分控制(I)，以消除穩態誤差。
上傳時間： 2014-07-21
上傳用戶：frank1234
Portable, battery-powered operation of electronic apparatushas become increasingly desirable. Medical, remotedata acquisition, power monitoring and other applicationsare good candidates for battery operation. In some circumstances,due to space, power or reliability considerations,it is preferable to operate the circuitry from a single 1.5Vcell. Unfortunately, a 1.5V supply eliminates almost alllinear ICs as design candidates. In fact, the LM10 opamp-reference and the LT®1017/LT1018 comparators arethe only IC gain blocks fully specifi ed for 1.5V operation.Further complications are presented by the 600mV dropof silicon transistors and diodes. This limitation consumesa substantial portion of available supply range, makingcircuit design diffi cult. Additionally, any circuit designedfor 1.5V operation must function at end-of-life batteryvoltage, typically 1.3V. (See Box Section, “Componentsfor 1.5V Operation.”)
標簽： Circuitry Operation Single 1017
上傳時間： 2013-12-20
上傳用戶：Wwill
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
上傳時間： 2013-11-12
上傳用戶：pans0ul
第一步，拿到一塊PCB，首先在紙上記錄好所有元氣件的型號，參數，以及位置，尤其是二極管，三極管的方向，IC缺口的方向。最好用數碼相機拍兩張元氣件位置的照片。 第二步，拆掉所有器件，并且將PAD孔里的錫去掉。用酒精將PCB清洗干凈，然后放入掃描儀內，啟動POHTOSHOP，用彩色方式將絲印面掃入，并打印出來備用。 第三步，用水紗紙將TOP LAYER 和BOTTOM LAYER兩層輕微打磨，打磨到銅膜發亮，放入掃描儀，啟動PHOTOSHOP，用彩色方式將兩層分別掃入。注意，PCB在掃描儀內擺放一定要橫平樹直，否則掃描的圖象就無法使用，掃描儀分辨率請選為600。 需要的朋友請下載哦！
上傳時間： 2013-11-17
上傳用戶：zhuimenghuadie
