The PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.
上傳時(shí)間： 2013-11-01
上傳用戶(hù)：KSLYZ
6小時(shí)學(xué)會(huì)labview, labview Six Hour Course – Instructor Notes This zip file contains material designed to give students a working knowledge of labview in a 6 hour timeframe. The contents are: Instructor Notes.doc – this document. labviewIntroduction-SixHour.ppt – a PowerPoint presentation containing screenshots and notes on the topics covered by the course. Convert C to F (Ex1).vi – Exercise 1 solution VI. Convert C to F (Ex2).vi – Exercise 2 solution subVI. Thermometer-DAQ (Ex2).vi – Exercise 2 solution VI. Temperature Monitor (Ex3).vi – Exercise 3 solution VI. Thermometer (Ex4).vi – Exercise 4 solution subVI. Convert C to F (Ex4).vi – Exercise 4 solution subVI. Temperature Logger (Ex4).vi – Exercise 4 solution VI. Multiplot Graph (Ex5).vi – Exercise 5 solution VI. Square Root (Ex6).vi – Exercise 6 solution VI. State Machine 1 (Ex7).vi – Exercise 7 solution VI. The slides can be presented in two three hour labs, or six one hour lectures. Depending on the time and resources available in class, you can choose whether to assign the exercises as homework or to be done in class. If you decide to assign the exercises in class, it is best to assign them in order with the presentation. This way the students can create VI’s while the relevant information is still fresh. The notes associated with the exercise slide should be sufficient to guide the students to a solution. The solution files included are one possible solution, but by no means the only solution.
標(biāo)簽： labview
上傳時(shí)間： 2013-10-13
上傳用戶(hù)：zjwangyichao
該系統(tǒng)以計(jì)算機(jī)為依托構(gòu)建中央信息處理系統(tǒng)CIPS（Central Information Processing System），以Pocket PC作為巡檢終端PS（Portable Station），采用SQL Server 2000關(guān)系型數(shù)據(jù)庫(kù)和SQL Server CE3.0嵌入式數(shù)據(jù)庫(kù)技術(shù)，集RFID技術(shù)、GPS定位技術(shù)、信息管理、信息傳輸?shù)榷囗?xiàng)技術(shù)于一體，完成信息在CIPS和PS之間的交互，實(shí)現(xiàn)巡檢信息的綜合處理。
標(biāo)簽： RFID GPS 智能巡檢系統(tǒng)
上傳時(shí)間： 2013-11-16
上傳用戶(hù)：stvnash
This document is a quick reference to some of the formulas and important information related to optical technologies. It focuses on decibels (dB), decibels per milliwatt (dBm), attenuation and measurements, and provides an introduction to optical fibers.
上傳時(shí)間： 2013-10-17
上傳用戶(hù)：libenshu01
同步技術(shù)是跳頻通信系統(tǒng)的關(guān)鍵技術(shù)之一，尤其是在快速跳頻通信系統(tǒng)中，常規(guī)跳頻通信通過(guò)同步字頭攜帶相關(guān)碼的方法來(lái)實(shí)現(xiàn)同步，但對(duì)于快跳頻來(lái)說(shuō)，由于是一跳或者多跳傳輸一個(gè)調(diào)制符號(hào)，難以攜帶相關(guān)碼。對(duì)此引入雙跳頻圖案方法，提出了一種適用于快速跳頻通信系統(tǒng)的同步方案。采用短碼攜帶同步信息，克服了快速跳頻難以攜帶相關(guān)碼的困難。分析了同步性能，仿真結(jié)果表明該方案同步時(shí)間短、虛警概率低、捕獲概率高，同步性能可靠。 Abstract: Synchronization is one of the key techniques to frequency-hopping communication system， especially in the fast frequency hopping communication system. In conventional frequency hopping communication systems， synchronization can be achieved by synchronization-head which can be used to carry the synchronization information， but for the fast frequency hopping， Because modulation symbol is transmitted by per hop or multi-hop， it is difficult to carry the correlation code. For the limitation of fast frequency hopping in carrying correlation code， a fast frequency-hopping synchronization scheme with two hopping patterns is proposed. The synchronization information is carried by short code， which overcomes the difficulty of correlation code transmission in fast frequency-hopping. The performance of the scheme is analyzed， and simulation results show that the scheme has the advantages of shorter synchronization time， lower probability of false alarm， higher probability of capture and more reliable of synchronization.
標(biāo)簽： 快速跳頻 同步技術(shù) 通信系統(tǒng)
上傳時(shí)間： 2013-11-23
上傳用戶(hù)：mpquest
The information in this specification is subject to change without notice.Use of this specification for product design requires an executed license agreement from the CompactFlashAssociation.The CompactFlash Association shall not be liable for technical or editorial errors or omissions contained herein; norfor incidental or consequential damages resulting from the furnishing, performance, or use of this material.All parts of the CompactFlash Specification are protected by copyright law and all rights are reserved. Thisdocumentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to anyelectronic medium or machine readable form without prior consent, in writing, from the CompactFlash Association.The CFA logo is a trademark of the CompactFlash Association.Product names mentioned herein are for identification purposes only and may be trademarks and/or registeredtrademarks of their respective companies.© 1998-99, CompactFlash Association. All rights reserved.
標(biāo)簽： 技術(shù)資料
上傳時(shí)間： 2013-10-08
上傳用戶(hù)：stewart·
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時(shí)間： 2014-01-17
上傳用戶(hù)：Altman
This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish reliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use.
上傳時(shí)間： 2014-12-31
上傳用戶(hù)：PresidentHuang
飛思卡爾智能車(chē)的舵機(jī)測(cè)試程序 #include <hidef.h> /* common defines and macros */#include <MC9S12XS128.h> /* derivative information */#pragma LINK_INFO DERIVATIVE "mc9s12xs128" void SetBusCLK_16M(void) { CLKSEL=0X00; PLLCTL_PLLON=1; //鎖相環(huán)電路允許位 SYNR=0x00 | 0x01; //SYNR=1 REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK==1)); CLKSEL_PLLSEL =1; } void PWM_01(void) { //舵機(jī)初始化 PWMCTL_CON01=1; //0和1聯(lián)合成16位PWM； PWMCAE_CAE1=0; //選擇輸出模式為左對(duì)齊輸出模式 PWMCNT01 = 0; //計(jì)數(shù)器清零； PWMPOL_PPOL1=1; //先輸出高電平，計(jì)數(shù)到DTY時(shí)，反轉(zhuǎn)電平 PWMPRCLK = 0X40; //clockA 不分頻,clockA=busclock=16MHz;CLK B 16分頻:1Mhz PWMSCLA = 0x08; //對(duì)clock SA 16分頻,pwm clock=clockA/16=1MHz; PWMCLK_PCLK1 = 1; //選擇clock SA做時(shí)鐘源 PWMPER01 = 20000; //周期20ms； 50Hz; PWMDTY01 = 1500; //高電平時(shí)間為1.5ms; PWME_PWME1 = 1;
標(biāo)簽： 飛思卡爾智能車(chē) 舵機(jī) 測(cè)試程序
上傳時(shí)間： 2013-11-04
上傳用戶(hù)：狗日的日子
IBIS 模型在做類(lèi)似板級(jí)SI 仿真得到廣泛應(yīng)用。在做仿真的初級(jí)階段，經(jīng)常對(duì)于ibis 模型的描述有些疑問(wèn)，只知道把模型拿來(lái)轉(zhuǎn)換為軟件所支持的格式或者直接使用，而對(duì)于IBIS 模型里面的數(shù)據(jù)描述什么都不算很明白，因此下面的一些描述是整理出來(lái)的一點(diǎn)對(duì)于ibis 的基本理解。在此引用很多presention來(lái)描述ibis 內(nèi)容（有的照抄過(guò)來(lái)，阿彌陀佛，不要說(shuō)抄襲，只不過(guò)習(xí)慣信手拈來(lái)說(shuō)明一些問(wèn)題），僅此向如muranyi 等ibis 先驅(qū)者致敬。本文難免有些錯(cuò)誤或者考慮不周，隨時(shí)歡迎進(jìn)行討論并對(duì)其進(jìn)行修改！IBIS 模型的一些基本概念I(lǐng)BIS 這個(gè)詞是Input/Output buffer information specification 的縮寫(xiě)。本文是基于IBIS ver3.2 所撰寫(xiě)出來(lái)（www.eigroup.org/IBIS/可下載到各種版本spec）,ver4.2增加很多新特性，由于在目前設(shè)計(jì)中沒(méi)用到不予以討論。。。在業(yè)界經(jīng)常會(huì)把spice 模型描述為transistor model 是因?yàn)樗枋龊芏嚯娐芳?xì)節(jié)問(wèn)題。而把ibis 模型描述為behavioral model 是因?yàn)樗⒉幌髎pice 模型那樣描述電路的構(gòu)成，IBIS 模型描述的只不過(guò)是電路的一種外在表現(xiàn)，象個(gè)黑匣子一樣，輸入什么然后就得到輸出結(jié)果，而不需要了解里面驅(qū)動(dòng)或者接收的電路構(gòu)成。因此有所謂的garbage in, garbage out，ibis 模型的仿真精度依賴(lài)于模型的準(zhǔn)確度以及考慮的worse case，因此無(wú)論你的模型如何精確而考慮的worse case 不周全或者你考慮的worse case 如何周全而模型不精確，都是得不到較好的仿真精度。
上傳時(shí)間： 2013-10-16
上傳用戶(hù)：zhouli
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