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Re-mapping

  • LPC1300系列產(chǎn)品勘誤數(shù)據(jù)手冊(cè)

    On the LPC13xx, programming, erasure and re-programming of the on-chip flash can be performed using In-System Programming (ISP) via the UART serial port, and also, can be performed using In-Application Programming (IAP) calls directed by the end-user code. For In-System Programming (ISP) via the UART serial port, the ISP command handler (resides in the bootloader) allows erasure of one or more sector (s) of the on-chip flash memory.

    標(biāo)簽: 1300 LPC 勘誤 數(shù)據(jù)手冊(cè)

    上傳時(shí)間: 2013-12-13

    上傳用戶:lmq0059

  • Allegro FPGA System Planner中文介紹

      完整性高的FPGA-PCB系統(tǒng)化協(xié)同設(shè)計(jì)工具   Cadence OrCAD and Allegro FPGA System Planner便可滿足較復(fù)雜的設(shè)計(jì)及在設(shè)計(jì)初級(jí)產(chǎn)生最佳的I/O引腳規(guī)劃,并可透過FSP做系統(tǒng)化的設(shè)計(jì)規(guī)劃,同時(shí)整合logic、schematic、PCB同步規(guī)劃單個(gè)或多個(gè)FPGA pin的最佳化及l(fā)ayout placement,借由整合式的界面以減少重復(fù)在design及PCB Layout的測試及修正的過程及溝通時(shí)間,甚至透過最佳化的pin mapping、placement后可節(jié)省更多的走線空間或疊構(gòu)。   Specifying Design Intent   在FSP整合工具內(nèi)可直接由零件庫選取要擺放的零件,而這些零件可直接使用PCB內(nèi)的包裝,預(yù)先讓我們同步規(guī)劃FPGA設(shè)計(jì)及在PCB的placement。  

    標(biāo)簽: Allegro Planner System FPGA

    上傳時(shí)間: 2013-11-06

    上傳用戶:wwwe

  • Algorithms(算法概論)pdf

    This book evolved over the past ten years from a set of lecture notes developed while teaching the undergraduate Algorithms course at Berkeley and U.C. San Diego. Our way of teaching this course evolved tremendously over these years in a number of directions, partly to address our students' background (undeveloped formal skills outside of programming), and partly to reect the maturing of the eld in general, as we have come to see it. The notes increasingly crystallized into a narrative, and we progressively structured the course to emphasize the ?story line? implicit in the progression of the material. As a result, the topics were carefully selected and clustered. No attempt was made to be encyclopedic, and this freed us to include topics traditionally de-emphasized or omitted from most Algorithms books.

    標(biāo)簽: Algorithms 算法

    上傳時(shí)間: 2013-11-11

    上傳用戶:JamesB

  • 基于單片機(jī)的簡單電子琴(源代碼)

    簡單電子琴的51單片機(jī)程序 #include<reg51.h>       //包含51單片機(jī)寄存器定義的頭文件 sbit P14=P1^4;     //將P14位定義為P1.4引腳 sbit P15=P1^5;          //將P15位定義為P1.5引腳 sbit P16=P1^6;     //將P16位定義為P1.6引腳 sbit P17=P1^7;     //將P17位定義為P1.7引腳 unsigned char keyval;   //定義變量儲(chǔ)存按鍵值 sbit sound=P2^0;     //將sound定義為P2.0 unsigned int C;     //全局變量,儲(chǔ)存定時(shí)器的定時(shí)常數(shù) unsigned int f;     //全局變量,儲(chǔ)存音階的頻率 //以下是C調(diào)低音的音頻宏定義 #define l_dao 262     //將“l_dao”宏定義為低音“1”的頻率262Hz #define l_re 294     //將“l_re” 宏定義為低音“2”的頻率294Hz #define l_mi 330     //將“l_mi” 宏定義為低音“3”的頻率330Hz #define l_fa 349        //將“l_fa” 宏定義為低音“4”的頻率349Hz #define l_sao 392       //將“l_sao”宏定義為低音“5”的頻率392Hz #define l_la 440        //將“l_la” 宏定義為低音“6”的頻率440Hz #define l_xi 494        //將“l_xi” 宏定義為低音“7”的頻率494Hz //以下是C調(diào)中音的音頻宏定義 #define dao 523     //將“dao”宏定義為低音“1”的頻率Hz #define re 587 //將“re” 宏定義為低音“2”的頻率Hz #define mi 659 //將“mi” 宏定義為低音“3”的頻率Hz #define fa 698 //將“fa” 宏定義為低音“4”的頻率Hz #define sao 784 //將“sao”宏定義為低音“5”的頻率Hz #define la 880 //將“la” 宏定義為低音“6”的頻率Hz #define xi 988 //將“xi” 宏定義為低音“7”的頻率Hz

    標(biāo)簽: 單片機(jī) 電子琴 源代碼

    上傳時(shí)間: 2013-11-09

    上傳用戶:tian126vip

  • Allegro FPGA System Planner中文介紹

      完整性高的FPGA-PCB系統(tǒng)化協(xié)同設(shè)計(jì)工具   Cadence OrCAD and Allegro FPGA System Planner便可滿足較復(fù)雜的設(shè)計(jì)及在設(shè)計(jì)初級(jí)產(chǎn)生最佳的I/O引腳規(guī)劃,并可透過FSP做系統(tǒng)化的設(shè)計(jì)規(guī)劃,同時(shí)整合logic、schematic、PCB同步規(guī)劃單個(gè)或多個(gè)FPGA pin的最佳化及l(fā)ayout placement,借由整合式的界面以減少重復(fù)在design及PCB Layout的測試及修正的過程及溝通時(shí)間,甚至透過最佳化的pin mapping、placement后可節(jié)省更多的走線空間或疊構(gòu)。   Specifying Design Intent   在FSP整合工具內(nèi)可直接由零件庫選取要擺放的零件,而這些零件可直接使用PCB內(nèi)的包裝,預(yù)先讓我們同步規(guī)劃FPGA設(shè)計(jì)及在PCB的placement。  

    標(biāo)簽: Allegro Planner System FPGA

    上傳時(shí)間: 2013-10-19

    上傳用戶:shaojie2080

  • 使用Artix-7 FPGA 降低您的系統(tǒng)功耗與成本

    As businesses and consumers expect more fromportable electronics, the FPGA industry has beencompelled to re-think how it serves these low-power,cost-sensitive markets. Application classes like

    標(biāo)簽: Artix FPGA 功耗

    上傳時(shí)間: 2013-11-08

    上傳用戶:immanuel2006

  • 國外游戲開發(fā)者雜志1998年第十一期配套代碼

    國外游戲開發(fā)者雜志1998年第十一期配套代碼,包含Andrew Flavell關(guān)于MIP-mapping的文章的配套代碼,Stan Melax多邊形下降的例子代碼和Jeff Lander的關(guān)于IK的例子代碼

    標(biāo)簽: 1998 開發(fā)者 代碼

    上傳時(shí)間: 2014-01-23

    上傳用戶:趙云興

  • The CD Audio sample allows some non-SCSI2 CD ROMs to support audio operations by intercepting the re

    The CD Audio sample allows some non-SCSI2 CD ROMs to support audio operations by intercepting the relevant audio ioctls and translating them into the command block(s) expected by the non-compliant cdroms. It supports Plug and Play and Power Management, and is 64-bit compliant.

    標(biāo)簽: intercepting operations non-SCSI support

    上傳時(shí)間: 2014-01-03

    上傳用戶:ls530720646

  • The source code for "C++ Solutions". This book is a companion to the book that is widely recognized

    The source code for "C++ Solutions". This book is a companion to the book that is widely recognized as "the C++ bible": The C++ Programming Language (third edition) by Bjarne Stroustrup. If you re a programmer, Bjarne s book comes very highly recommended.

    標(biāo)簽: book recognized Solutions companion

    上傳時(shí)間: 2014-01-22

    上傳用戶:努力努力再努力

  • The cart with an inverted pendulum, shown below, is "bumped" with an impulse force, F. Determine th

    The cart with an inverted pendulum, shown below, is "bumped" with an impulse force, F. Determine the dynamic equations of motion for the system, and lin earize about the pendulum s angle, theta = Pi (in other words, assume that p endulum does not move more than a few degrees away from the vertical, chosen to be at an angle of Pi). Find a controller to satisfy all of the design re quirements given below.

    標(biāo)簽: F. with Determine inverted

    上傳時(shí)間: 2014-01-17

    上傳用戶:miaochun888

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