基于通用集成運(yùn)算放大器，利用MASON公式設(shè)計(jì)了一個(gè)多功能二階通用濾波器，能同時(shí)或分別實(shí)現(xiàn)低通、高通和帶通濾波，也能設(shè)計(jì)成一個(gè)正交振蕩器。電路的極點(diǎn)頻率和品質(zhì)因數(shù)能夠獨(dú)立、精確地調(diào)節(jié)。電路使用4個(gè)集成運(yùn)放、2個(gè)電容和11個(gè)電阻，所有集成運(yùn)放的反相端虛地。利用計(jì)算機(jī)仿真電路的通用濾波功能、極點(diǎn)頻率和品質(zhì)因數(shù)的獨(dú)立控制和正交正弦振蕩，從而證明該濾波器正確有效。 Abstract: A new multifunctional second-order filter based on OPs was Presented by MASON formula. Functions， such as high-pass， band-pass， low-pass filtering， can be realized respectively and simultaneously， and can become a quadrature oscillator by modifying resistance ratio. Its pole angular frequency and quality factor can be tuned accurately and independently. The circuit Presented contains four OPs， two capacitors， and eleven resistances， and inverting input of all OPs is virtual ground. Its general filtering， the independent control of pole frequency and quality factor and quadrature sinusoidal oscillation were simulated by computer， and the result shows that the Presented circuit is valid and effective.
標(biāo)簽： MASON 多功能 二階 濾波器設(shè)計(jì)
上傳時(shí)間： 2013-10-09
上傳用戶：13788529953
This application note discusses a variety of approaches for interfacing analog signals to 5V powered systems. Synthesizing a "rail-to-rail" op amp and scaling techniques for A/D converters are covered. A voltage-to-frequency converter, applicable where high resolution is required, is also Presented.
標(biāo)簽： 微處理器 系統(tǒng)接口
上傳時(shí)間： 2013-10-12
上傳用戶：181992417
介紹了以PLC為控制單元，變頻器為執(zhí)行單元的控制系統(tǒng)及其在煙支輸送儲(chǔ)存系統(tǒng)中的應(yīng)用，并給出了系統(tǒng)的組成、硬件的配置及具體的實(shí)現(xiàn)方法。關(guān)鍵詞 : PLC 變頻器輸送儲(chǔ)存系統(tǒng) Ab str ac t;T hisp aperi ntroducest hec ontrols ystem whichc onsistso fP LCa ndf requencyc onvertera ndi ts application in the buffer conveyor for cigarettes. The system constitute, hardware disposal and realization method are also Presented in detail.Keywords:PLC f requencyc onverter b ufferc onveyor
標(biāo)簽： PLC 變頻器 中的應(yīng)用 存儲(chǔ)系統(tǒng)
上傳時(shí)間： 2013-10-22
上傳用戶：ouyang426
基于基本遺傳算法的函數(shù)最優(yōu)化SGA.C A Function Optimizer using Simple Genetic Algorithm developed from the Pascal SGA code Presented by David E.Goldberg
標(biāo)簽： Algorithm Optimizer developed Function
上傳時(shí)間： 2015-05-29
上傳用戶：aa54
This application note describes a method for developing block-oriented I/O device drivers for applications that use the DSP/BIOS real-time kernel and includes examples that run with Code Composer Studio v2.1 on the Texas Instruments TMS320C5402 and TMS320C6711 DSP Starter Kits (DSKs). The device driver model Presented here has now been superceded with an updated version that supports not only block oriented devices, but also devices such as UARTs, PCI and USB buses and Multimedia cards. Documentation on the updated driver model as well as example drivers and source code can be found in the Device Driver Developer s Kit product now available for download from the TI Developer s Village.
標(biāo)簽： block-oriented application developing describes
上傳時(shí)間： 2015-07-07
上傳用戶：kelimu
Most code samples included on this CD were developed with Microsoft Visual C++ version 5.0 and the Microsoft Windows CE Toolkit for Visual C++ version 5.0. The Sspi and Crypto samples were developed with Microsoft Visual C++ version 6.0 and the Microsoft Windows CE Toolkit for Visual C++ 6.0. The code in sample applications is ported for a Handheld PC, but the programming concepts that are Presented apply to all Windows CE-based platforms.
標(biāo)簽： Microsoft developed included samples
上傳時(shí)間： 2015-07-10
上傳用戶：Pzj
關(guān)于FPGA流水線設(shè)計(jì)的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is Presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標(biāo)簽： investigates implementing pipelines circuits
上傳時(shí)間： 2015-07-26
上傳用戶：CHINA526
THIS is really two books in one: a tutorial and a reference manual for JDBC, the application programming interface that makes it possible for programmers to access databases from Java. The goal is to be useful to a wide range of readers, from database novices to database experts. Therefore, we have arranged the book so that information needed only by experts is separated out from the basic material. We hope that driver developers as well as application programmers and MIS administrators will find what they need. Because different sections are aimed at different audiences, we expect that few people will read every page. We have sometimes duplicated explanations in an effort to make reading easier for those who do not read all sections. This book will be most helpful to those who have some knowledge of the Java programming language and SQL (Structured Query Language), but one doesn t need to be an expert in either to understand the basic concepts Presented here.
標(biāo)簽： application reference tutorial program
上傳時(shí)間： 2015-08-04
上傳用戶：zhengzg
Verilog and VHDL狀態(tài)機(jī)設(shè)計(jì)，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding Presented. Different methodologies will be compared using real-world examples.
標(biāo)簽： Verilog VHDL and 狀態(tài)
上傳時(shí)間： 2013-12-19
上傳用戶：change0329
An approach to reengineer BASIC PC legacy code into modern graphical systems is proposed.BASIC peculiarities are Presented and discussed, with preliminary results on code translation.
標(biāo)簽： BASIC reengineer graphical approach
上傳時(shí)間： 2014-01-05
上傳用戶：zhaiye
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