PCi總線是目前最為流行的一種局部性總線 通過(guò)對(duì)PCi總線一些典型功能的分析以及時(shí)序的闡述，利用VetilogHDL設(shè)計(jì)了一個(gè)將非PCi功能設(shè)備轉(zhuǎn)接到PC1總線上的IP Core 同時(shí)，通過(guò)在ModeISim SE PLUS 6．0 上運(yùn)行測(cè)試程序模塊，得到了理想的仿真數(shù)據(jù)波形，從軟件上證明了功能的實(shí)現(xiàn)。
標(biāo)簽： VeriIog Core PCi HDL
上傳時(shí)間： 2014-12-30
上傳用戶：himbly
The PCi Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCi Special Interest Group make a commitment to update the information contained herein.
上傳時(shí)間： 2013-11-01
上傳用戶：KSLYZ
作為一種獨(dú)立于處理器的局部總線,PCi非常適用于網(wǎng)絡(luò)適配器、硬盤(pán)驅(qū)動(dòng)器、全動(dòng)態(tài)視頻卡、圖形卡及各類高速外設(shè)。據(jù)稱,目前有90%的Pentium處理器采用PCi做為系統(tǒng)總線。
上傳時(shí)間： 2013-11-07
上傳用戶：liaocs77
PCi Express是由Intel，Dell，Compaq，IBM，Microsoft等PCi SIG聯(lián)合成立的Arapahoe Work Group共同草擬并推舉成取代PCi總線標(biāo)準(zhǔn)的下一代標(biāo)準(zhǔn)。PCi Express利用串行的連接特點(diǎn)能輕松將數(shù)據(jù)傳輸速度提到一個(gè)很高的頻率，達(dá)到遠(yuǎn)遠(yuǎn)超出PCi總線的傳輸速率。一個(gè)PCi Express連接可以被配置成x1，x2，x4，x8，x12，x16和x32的數(shù)據(jù)帶寬。x1的通道能實(shí)現(xiàn)單向312.5 MB／s（2.5 Gb／s）的傳輸速率。Xilinx公司的Virtex5系列FPGA芯片內(nèi)嵌PCi-ExpressEndpoint Block硬核，為實(shí)現(xiàn)單片可配置PCi-Express總線解決方案提供了可能。 本文在研究PCi-Express接口協(xié)議和PCi-Express Endpoint Block硬核的基礎(chǔ)上，使用Virtex5LXT50 FPGA芯片設(shè)計(jì)PCi Express接口硬件電路，實(shí)現(xiàn)PCi-Express數(shù)據(jù)傳輸
上傳時(shí)間： 2013-12-27
上傳用戶：wtrl
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCi-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCi-X target initial latency specification. PCi-X Protocol Addendum tothe PCi Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCitermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCi-X busfrequency. However, this solution increases the required power and clock resource usage.
上傳時(shí)間： 2013-11-24
上傳用戶：18707733937
PCi-PCi 橋啟動(dòng)時(shí)，一般需要從EEPROM 預(yù)讀取配置數(shù)據(jù)。更改EEPROM中的數(shù)據(jù)一般需要專用的燒結(jié)器，這給調(diào)試過(guò)程帶來(lái)不便。尤其是采用表貼封裝的EEPROM。本文以Intel 公司的Dec21554PCi-PCi 橋?yàn)槔榻B一種在線讀寫(xiě)EEPROM 的方法。EEPROM選用的是ATMEL 公司生產(chǎn)的AT93LC66，4Kbit，按512×8bit 組織。
標(biāo)簽： PCi-PCi EEPROM 在線讀寫(xiě)
上傳時(shí)間： 2013-11-08
上傳用戶：trepb001
This document provides practical, common guidelines for incorporating PCi Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCi Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCi Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCi Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： PCi PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2014-01-24
上傳用戶：s363994250
PCi-E是一種高速傳輸總線形式。
標(biāo)簽： PCi-E 8622 數(shù)據(jù)采集卡
上傳時(shí)間： 2013-12-18
上傳用戶：宋桃子
PCi-1734快速安裝使用手冊(cè)PCi-1734快速安裝使用手冊(cè)PCi-1734快速安裝使用手冊(cè)PCi-1734快速安裝使用手冊(cè)PCi-1734快速安裝使用手冊(cè)PCi-1734快速安裝使用手冊(cè)PCi-1734快速安裝使用手冊(cè)
上傳時(shí)間： 2013-10-22
上傳用戶：ssz1990
本文介紹一種基于PCi Express 總線的高速數(shù)據(jù)采集卡的設(shè)計(jì)方案及功能實(shí)現(xiàn)。給出系統(tǒng)的基本結(jié)構(gòu)及單元組成，重點(diǎn)闡述系統(tǒng)硬件設(shè)計(jì)的關(guān)鍵技術(shù)和本地總線的控制邏輯，詳細(xì)探討了基于DriverWorks 的設(shè)備驅(qū)動(dòng)程序的開(kāi)發(fā)以及上層應(yīng)用軟件的設(shè)計(jì)。該系統(tǒng)通過(guò)實(shí)踐驗(yàn)證，可用于衛(wèi)星下行高速數(shù)據(jù)的接收并可適用于其他高速數(shù)據(jù)采集與處理系統(tǒng)。關(guān)鍵詞：PCi Express 總線 PCiE PEX8311 DMA 板卡驅(qū)動(dòng) 隨著空間科學(xué)和空間電子學(xué)技術(shù)的飛速發(fā)展，空間科學(xué)實(shí)驗(yàn)的種類和數(shù)量以及科學(xué)實(shí)驗(yàn)所產(chǎn)生的數(shù)據(jù)量不斷增加。為了使地面接收處理系統(tǒng)能夠?qū)崟r(shí)處理和顯示科學(xué)圖像數(shù)據(jù)，必須要設(shè)計(jì)出新的地面數(shù)據(jù)接收處理系統(tǒng)，實(shí)現(xiàn)大量高速數(shù)據(jù)的正確接收采集、處理以及存儲(chǔ)。為了滿足地面系統(tǒng)的要求，并為以后的計(jì)算機(jī)系統(tǒng)升級(jí)提供更廣闊的空間，本系統(tǒng)擬采用第三代I/O 互連技術(shù)PCi Express（簡(jiǎn)稱PCi-E）作為本數(shù)據(jù)采集卡的進(jìn)機(jī)總線形式。本文通過(guò)對(duì)PCi-E 總線專用接口芯片PLX 公司的PEX8311 性能分析，特別是對(duì)突發(fā)讀、寫(xiě)和DMA讀操作的時(shí)序研究，設(shè)計(jì)出本地總線的可編程控制邏輯，并詳細(xì)討論了整個(gè)PCi-E 高速數(shù)據(jù)采集卡的硬件設(shè)計(jì)方案，以及WDM 驅(qū)動(dòng)程序和上層應(yīng)用程序的設(shè)計(jì)方法。
標(biāo)簽： Express PCi 總線 卡的設(shè)計(jì)
上傳時(shí)間： 2013-10-28
上傳用戶：tianyi996
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