PCi-E電氣規(guī)格標(biāo)準(zhǔn)
標(biāo)簽： PCi-E 電氣 規(guī)格標(biāo)準(zhǔn)
上傳時(shí)間： 2013-05-26
上傳用戶：eeworm
月球人的遊戲喔 AMD S3000+ 64Bit $2770 華碩 K8N4-E (PCi-E) $3100 華碩 N6200 TC256/128MBTOP $1890 BNEQ 1640 黑/白/銀 $1380 日立 sata 80G/8M 3年保固 $1580 創(chuàng)見(jiàn)DDR400 or 金士頓DDR400 512MB $1490
標(biāo)簽： PCi-E N6200 MBTOP 3000
上傳時(shí)間： 2013-12-23
上傳用戶：hustfanenze
DS+DDK+VC開發(fā)的適用于PCI、PCi-E的驅(qū)動(dòng)程序。
上傳時(shí)間： 2014-01-19
上傳用戶：蠢蠢66
PCi-E的驅(qū)動(dòng)程序例子,包含基本功能,可用于最初的測(cè)試
標(biāo)簽： PCi-E 驅(qū)動(dòng)程序 測(cè)試
上傳時(shí)間： 2016-09-28
上傳用戶：rocketrevenge
計(jì)算機(jī)接口通識(shí)大全,收集了計(jì)算機(jī)大部分通用接口,詳細(xì)介紹我們常用的接口的用途如USB IEEE1394 VGA DVI PCI PCi-E S_video 等近百種接口的定義 規(guī)格及參數(shù). 在華碩電腦工作快5年了,本人(任PE一職)做筆記本,在網(wǎng)上收集了些資料,自己工作之余做了一下整理,本來(lái)是用來(lái)給新近員工做基礎(chǔ)教育用的,現(xiàn)拿出來(lái)分享,同大家一起學(xué)習(xí)計(jì)算機(jī)通用接口,有錯(cuò)誤之處還請(qǐng)大家到本人網(wǎng)站留言指出,謝謝!
標(biāo)簽： S_video PCi-E IEEE 1394
上傳時(shí)間： 2017-03-29
上傳用戶：ghostparker
PCi-E接口設(shè)計(jì)是現(xiàn)在系統(tǒng)設(shè)計(jì)的熱點(diǎn)，本文檔是在xilinx芯片中集成pcie接口控制器的好資料
標(biāo)簽： PCi-E 接口設(shè)計(jì) 系統(tǒng)設(shè)計(jì)
上傳時(shí)間： 2017-08-14
上傳用戶：yoleeson
RTL8111E是瑞昱的PCi-E接口千兆以太網(wǎng)芯片。引腳從48個(gè)，外圍電路簡(jiǎn)單，不需要外部EEPROM，MAC地址燒寫更加方便。
標(biāo)簽： rtl8111e PCi-E 接口 以太網(wǎng)
上傳時(shí)間： 2021-12-11
上傳用戶：jiabin
基于SPARTAN-6的PCi-E開發(fā)板原理圖
上傳時(shí)間： 2022-06-18
上傳用戶：
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2013-10-15
上傳用戶：busterman
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2014-01-24
上傳用戶：s363994250
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