中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
上傳時間： 2013-10-27
上傳用戶：zoudejile
針對傳統集成電路（ASIC）功能固定、升級困難等缺點，利用FPGA實現了擴頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實現NCO模塊，在下變頻模塊調用了硬核乘法器并引入CIC濾波器進行低通濾波，給出了DQPSK解調的原理和實現方法，推導出一種簡便的引入?仔/4固定相移的實現方法。采用模塊化的設計方法使用VHDL語言編寫出源程序，在Virtex-II Pro 開發板上成功實現了整個系統。測試結果表明該系統正確實現了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
上傳時間： 2013-11-06
上傳用戶：liu123
GPRS模塊程序
上傳時間： 2013-11-17
上傳用戶：woshini123456
USI WiFi module specification
標簽： Specification WM-G-MR WiFi 09
上傳時間： 2013-11-20
上傳用戶：y13567890
無線模塊（RF wireless module）是利用無線技術進行無線傳輸的一種模塊。它被廣泛地應用于電腦無線網絡，無線通訊，無線控制等領域。無線模塊主要由發射器，接收器和控制器組成。 無線數據傳輸廣泛地運用在車輛監控、遙控、遙測、小型無線網絡、無線抄表、門禁系統、小區傳呼、工業數據采集系統、無線標簽、身份識別、非接觸RF智能卡、小型無線數據終端、安全防火系統、無線遙控系統、生物信號采集、水文氣象監控、機器人控制、無線232數據通信、無線485/422數據通信、數字音頻、數字圖像傳輸等領域中。 該方案由成都江騰科技有限公司（http://www.jiangteng-tech.com/）提供，是無線通信的最佳選擇。內附無線模塊參數設置軟件，可對串口波特率、空中速率、RF頻率、頻道號、輸出功率等參數輕松設置。
上傳時間： 2014-12-29
上傳用戶：fudong911
該對講機模塊是一款性價比極高的全集成對講機Module，內置高性能射頻收發芯片、微控制器以及射頻功放(PA)。外部控制器通過標準的異步串行接口（RS232）設置模塊的參數、功能，并可通過串口AT指令控制整個模塊的收發。 該模塊體積小、集成度高、性能穩定、應用靈活，且符合世界大多數國家對講機標準，很容易通過CE/FCC等認證；采用此模塊可做成小型對講機，也可將模塊嵌入到其它手持終端設備以實現無線對講功能。
上傳時間： 2013-11-25
上傳用戶：caoyuanyuan1818
The Tri-Mode Ethernet MAC (TEMAC) UltraController-II module is a minimal footprint,embedded network processing engine based on the PowerPC™ 405 (PPC405) processor coreand the TEMAC core embedded within a Virtex™-4 FX Platform FPGA. The TEMACUltraController-II module connects to an external PHY through Gigabit Media IndependentInterface (GMII) and Management Data Input/Output (MDIO) interfaces and supports tri-mode(10/100/1000 Mb/s) Ethernet. Software running from the processor cache reads and writesthrough an On-Chip Memory (OCM) interface to two FIFOs that act as buffers between thedifferent clock domains of the PPC405 OCM and the TEMAC.
上傳時間： 2013-10-26
上傳用戶：yuzsu
為提升虛擬儀器傳輸速率與實時性能，擴展監測范圍，在VC的軟件平臺上設計了一種全功能虛擬示波器。與傳統虛擬示波器相比，該系統采用嵌入式系統完成信號采集，采用工業以太網為傳輸介質，通過線性插值算法和多線程編程思想，實現波形顯示、參數計算、頻譜分析以及波形存儲及回放功能。實驗結果表明，該虛擬示波器可以實現20 kHz采樣頻率下的波形精確顯示，達到預期的各項指標。 Abstract: o enhance the transfer rate and real-time of virtual instrument performance， expand scope of monitoring， this paper uses the VCs software platform to design a fully functional virtual oscilloscope. Compared with traditional virtual oscilloscope， this system adopts the embedded system to complete the data acquisition， industrial Ethernet as the transmission medium used by the linear interpolation algorithm and multi-threaded programming ideas， namely to achieve waveform display， parameter calculation， spectrum analysis and waveform storage and playback. Experimental results show that the virtual oscilloscope can accurately display the waveform with 20kHz sampling frequency， and achieve the desired targets.
上傳時間： 2013-11-25
上傳用戶：wbwyl
zigbee module ,arm cortex m3 ,soc
上傳時間： 2013-10-13
上傳用戶：hsfei8
