The RT9005A/B is a dual-output Linear regulator for DDR-SDRAM VDDQ supply and termination voltage VTT supply.
上傳時(shí)間： 2013-11-13
上傳用戶：lmq0059
The RT9018A/B is a high performance positive voltage regulator designed for use in applications requining very low Input voltage and very low dropout voltage at up to 3A(peak).
上傳時(shí)間： 2013-10-10
上傳用戶：geshaowei
本軟件是關(guān)于MAX338, MAX339的英文數(shù)據(jù)手冊(cè)：MAX338, MAX339 8通道/雙4通道、低泄漏、CMOS模擬多路復(fù)用器 The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions. These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.
上傳時(shí)間： 2013-11-12
上傳用戶：18711024007
This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
上傳時(shí)間： 2013-10-31
上傳用戶：yy_cn
溫濕度傳感器 sht11 仿真程序 sbit out =P3^0; //加熱口 //sbit input =P1^1;//檢測(cè)口 //sbit speek =P2^0;//報(bào)警 sbit clo =P3^7;//時(shí)鐘 sbit ST =P3^5;//開(kāi)始 sbit EOC =P3^6;//成功信號(hào) sbit gwei =P3^4;//個(gè)位 sbit swei =P3^3;//十位 sbit bwei =P3^2;//百位 sbit qwei =P3^1;//千位 sbit speak =P0^0;//報(bào)警音 sbit bjled =P0^1;//報(bào)警燈 sbit zcled =P0^2;//正常LED int count; uchar xianzhi;//取轉(zhuǎn)換結(jié)果 uchar seth;//高時(shí)間 uchar setl;//低時(shí)間 uchar seth_mi;//高時(shí)間 uchar setl_mi;//低時(shí)間 bit hlbz;//高低標(biāo)志 bit clbz; bit spbz; ///定時(shí)中斷程序/// void t0 (void) interrupt 1 using 0 { TH0=(65536-200)/256;//5ms*200=1000ms=1s TL0=(65536-200)%256; clo=!clo;//產(chǎn)生時(shí)鐘 if(count>5000) { if(hlbz) { if(seth_mi==0){seth_mi=seth;hlbz=0;out=0;} else seth_mi--; } if(!hlbz) { if(setl_mi==0){setl_mi=setl;hlbz=1;out=1;} else setl_mi--; } count=0; } else count++; } ///////////// ///////延時(shí)/////// delay(int i) { while(--i); } ///////顯示處理/////// xianshi() { int abcd=0; int i; for (i=0;i<5;i++) { abcd=xianzhi; gwei=1; swei=1; bwei=1; qwei=1; P1=dispcode[abcd/1000]; qwei=0; delay(70); qwei=1; abcd=abcd%1000; P1=dispcode[abcd/100]; bwei=0; delay(70); bwei=1; abcd=abcd%100; P1=dispcode[abcd/10]; swei=0; delay(70); swei=1; abcd=abcd%10; P1=dispcode[abcd]; gwei=0; delay(70); gwei=1; } } doing() { if(xianzhi>100) {bjled=0;speak=1;zcled=1;} else {bjled=1;speak=0;zcled=0;} } void main(void) { seth=60;//h60秒 setl=90;//l90秒 seth_mi=60;//h60秒 setl_mi=90;//l90秒 TMOD=0X01;//定時(shí)0 16位工作模式 TH0=(65536-200)/256; TL0=(65536-200)%256; TR0=1; //開(kāi)始計(jì)時(shí) ET0=1; //開(kāi)定時(shí)0中斷 EA=1; //開(kāi)全中斷 while(1) { ST=0; _nop_(); ST=1; _nop_(); ST=0; // EOC=0; xianshi(); while(!EOC) { xianshi(); } xianzhi=P2; xianshi(); doing(); } }
上傳時(shí)間： 2013-11-07
上傳用戶：我們的船長(zhǎng)
注:1.這篇文章斷斷續(xù)續(xù)寫了很久,畫(huà)圖技術(shù)也不精,難免錯(cuò)漏,大家湊合看.有問(wèn)題可以留言. 2.論壇排版把我的代碼縮進(jìn)全弄沒(méi)了,大家將代碼粘貼到arduino編譯器,然后按ctrl+T重新格式化代碼格式即可看的舒服. 一、什么是PWM PWM 即Pulse Wavelength Modulation 脈寬調(diào)制波，通過(guò)調(diào)整輸出信號(hào)占空比，從而達(dá)到改 變輸出平均電壓的目的。相信Arduino 的PWM 大家都不陌生，在Arduino Duemilanove 2009 中，有6 個(gè)8 位精度PWM 引腳，分別是3, 5, 6, 9, 10, 11 腳。我們可以使用analogWrite()控 制PWM 腳輸出頻率大概在500Hz 的左右的PWM 調(diào)制波。分辨率8 位即2 的8 次方等于 256 級(jí)精度。但是有時(shí)候我們會(huì)覺(jué)得6 個(gè)PWM 引腳不夠用。比如我們做一個(gè)10 路燈調(diào)光， 就需要有10 個(gè)PWM 腳。Arduino Duemilanove 2009 有13 個(gè)數(shù)字輸出腳，如果它們都可以 PWM 的話，就能滿足條件了。于是本文介紹用軟件模擬PWM。 二、Arduino 軟件模擬PWM Arduino PWM 調(diào)壓原理：PWM 有好幾種方法。而Arduino 因?yàn)殡娫春蛯?shí)現(xiàn)難度限制，一般 使用周期恒定，占空比變化的單極性PWM。 通過(guò)調(diào)整一個(gè)周期里面輸出腳高/低電平的時(shí)間比（即是占空比）去獲得給一個(gè)用電器不同 的平均功率。 如圖所示，假設(shè)PWM 波形周期1ms（即1kHz），分辨率1000 級(jí)。那么需要一個(gè)信號(hào)時(shí)間 精度1ms/1000=1us 的信號(hào)源，即1MHz。所以說(shuō)，PWM 的實(shí)現(xiàn)難點(diǎn)在于需要使用很高頻的 信號(hào)源，才能獲得快速與高精度。下面先由一個(gè)簡(jiǎn)單的PWM 程序開(kāi)始： const int PWMPin = 13; int bright = 0; void setup() { pinMode(PWMPin, OUTPUT); } void loop() { if((bright++) == 255) bright = 0; for(int i = 0; i < 255; i++) { if(i < bright) { digitalWrite(PWMPin, HIGH); delayMicroseconds(30); } else { digitalWrite(PWMPin, LOW); delayMicroseconds(30); } } } 這是一個(gè)軟件PWM 控制Arduino D13 引腳的例子。只需要一塊Arduino 即可測(cè)試此代碼。 程序解析：由for 循環(huán)可以看出，完成一個(gè)PWM 周期，共循環(huán)255 次。 假設(shè)bright=100 時(shí)候，在第0~100 次循環(huán)中，i 等于1 到99 均小于bright，于是輸出PWMPin 高電平； 然后第100 到255 次循環(huán)里面，i 等于100~255 大于bright，于是輸出PWMPin 低電平。無(wú) 論輸出高低電平都保持30us。 那么說(shuō)，如果bright=100 的話，就有100 次循環(huán)是高電平，155 次循環(huán)是低電平。 如果忽略指令執(zhí)行時(shí)間的話，這次的PWM 波形占空比為100/255，如果調(diào)整bright 的值， 就能改變接在D13 的LED 的亮度。 這里設(shè)置了每次for 循環(huán)之后，將bright 加一，并且當(dāng)bright 加到255 時(shí)歸0。所以，我們 看到的最終效果就是LED 慢慢變亮，到頂之后然后突然暗回去重新變亮。 這是最基本的PWM 方法，也應(yīng)該是大家想的比較多的想法。 然后介紹一個(gè)簡(jiǎn)單一點(diǎn)的。思維風(fēng)格完全不同。不過(guò)對(duì)于驅(qū)動(dòng)一個(gè)LED 來(lái)說(shuō)，效果與上面 的程序一樣。 const int PWMPin = 13; int bright = 0; void setup() { pinMode(PWMPin, OUTPUT); } void loop() { digitalWrite(PWMPin, HIGH); delayMicroseconds(bright*30); digitalWrite(PWMPin, LOW); delayMicroseconds((255 - bright)*30); if((bright++) == 255) bright = 0; } 可以看出，這段代碼少了一個(gè)For 循環(huán)。它先輸出一個(gè)高電平，然后維持(bright*30)us。然 后輸出一個(gè)低電平，維持時(shí)間((255-bright)*30)us。這樣兩次高低就能完成一個(gè)PWM 周期。 分辨率也是255。 三、多引腳PWM Arduino 本身已有PWM 引腳并且運(yùn)行起來(lái)不占CPU 時(shí)間，所以軟件模擬一個(gè)引腳的PWM 完全沒(méi)有實(shí)用意義。我們軟件模擬的價(jià)值在于：他能將任意的數(shù)字IO 口變成PWM 引腳。 當(dāng)一片Arduino 要同時(shí)控制多個(gè)PWM，并且沒(méi)有其他重任務(wù)的時(shí)候，就要用軟件PWM 了。 多引腳PWM 有一種下面的方式： int brights[14] = {0}; //定義14個(gè)引腳的初始亮度，可以隨意設(shè)置 int StartPWMPin = 0, EndPWMPin = 13; //設(shè)置D0~D13為PWM 引腳 int PWMResolution = 255; //設(shè)置PWM 占空比分辨率 void setup() { //定義所有IO 端輸出 for(int i = StartPWMPin; i <= EndPWMPin; i++) { pinMode(i, OUTPUT); //隨便定義個(gè)初始亮度,便于觀察 brights[ i ] = random(0, 255); } } void loop() { //這for 循環(huán)是為14盞燈做漸亮的。每次Arduino loop()循環(huán)， //brights 自增一次。直到brights=255時(shí)候，將brights 置零重新計(jì)數(shù)。 for(int i = StartPWMPin; i <= EndPWMPin; i++) { if((brights[i]++) == PWMResolution) brights[i] = 0; } for(int i = 0; i <= PWMResolution; i++) //i 是計(jì)數(shù)一個(gè)PWM 周期 { for(int j = StartPWMPin; j <= EndPWMPin; j++) //每個(gè)PWM 周期均遍歷所有引腳 { if(i < brights[j])\ 所以我們要更改PWM 周期的話，我們將精度（代碼里面的變量：PWMResolution）降低就行，比如一般調(diào)整LED 亮度的話，我們用64 級(jí)精度就行。這樣速度就是2x32x64=4ms。就不會(huì)閃了。
上傳時(shí)間： 2013-10-08
上傳用戶：dingdingcandy
protel 99se 使用技巧以及常見(jiàn)問(wèn)題解決方法：里面有一些protel 99se 特別技巧，還有我們經(jīng)常遇到的一些問(wèn)題！如何使一條走線至兩個(gè)不同位置零件的距離相同? 您可先在Design/Rule/High Speed/Matched Net Lengths的規(guī)則中來(lái)新增規(guī)則設(shè)定,最后再用Tools/EqualizeNet Lengths 來(lái)等長(zhǎng)化即可。 Q02、在SCHLIB中造一零件其PIN的屬性，如何決定是Passive, Input, I/O, Hi- Z,Power,…..？在HELP中能找到說(shuō)明嗎？市面有關(guān) SIM？PLD？的書(shū)嗎？或貴公司有講義？ 你可在零件庫(kù)自制零件時(shí)點(diǎn)選零件Pin腳,并在Electrical Type里,可以自行設(shè)定PIN的 屬性,您可參考臺(tái)科大的Protel sch 99se 里面有介紹關(guān)于SIM的內(nèi)容。 Q03、請(qǐng)問(wèn)各位業(yè)界前輩,如何能順利讀取pcad8.6版的線路圖,煩請(qǐng)告知 Protel 99SE只能讀取P-CAD 2000的ASCII檔案格式,所以你必須先將P-CAD8.6版的格式轉(zhuǎn)為P-CAD 2000的檔案格式,才能讓Protel讀取。 Q04、請(qǐng)問(wèn)我該如何標(biāo)示線徑大小的那個(gè)平方呢 你可以將格點(diǎn)大小設(shè)小,還有將字形大小縮小,再放置數(shù)字的平方位置即可。 Q05、請(qǐng)問(wèn)我一次如何更改所有組件的字型 您可以點(diǎn)選其中一個(gè)組件字型,再用Global的方法就可以達(dá)成你的要求。
上傳時(shí)間： 2015-01-01
上傳用戶：yxgi5
Applying power to a standard logic chip, SRAM, or EPROM, usually results in output pinstracking the applied voltage as it rises. Programmable logic attempts to emulate that behavior,but physics forbids perfect emulation, due to the device programmability. It requires care tospecify the pin behavior, because programmable parts encounter unknown variables – yourdesign and your power environment.
標(biāo)簽： Xilinx XAPP CPLD 440
上傳時(shí)間： 2013-11-24
上傳用戶：253189838
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時(shí)間： 2014-11-26
上傳用戶：erkuizhang
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
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