中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
通過比較各種隔離數(shù)字通信的特點(diǎn)和應(yīng)用范圍，指出塑料光纖在隔離數(shù)字通信中的優(yōu)勢(shì)。使用已經(jīng)標(biāo)準(zhǔn)化的TOSLINK接口，有利于節(jié)省硬件開發(fā)成本和簡(jiǎn)化設(shè)計(jì)難度。給出了塑料光纖的硬件驅(qū)動(dòng)電路，說明設(shè)計(jì)過程中的注意事項(xiàng)，對(duì)光收發(fā)模塊的電壓特性和頻率特性進(jìn)行全面試驗(yàn)，并給出SPI口使用塑料光纖隔離通信的典型應(yīng)用電路圖。試驗(yàn)結(jié)果表明，該設(shè)計(jì)可為電力現(xiàn)場(chǎng)、電力電子及儀器儀表的設(shè)計(jì)提供參考。 Abstract: y comparing characteristics and applications area of various isolated digital communications， this article indicates advantages of plastic optical fiber in isolated digital communications. Using the standardized TOSLINK interface， it helps to control costs and difficulty in hardware development and design. Then it gives the hardware driver circuit of plastic optical fiber module， explains the noticed details in design process， gives results on the basis of the optical transceiver module voltage characteristics and frequency characteristics tests. Finally，it gives typical application circuit of the SPI communication port by using plastic optical fiber isolation .The results show that this design can be referenced for the power field， power electronics and instrumentation design.
標(biāo)簽： 塑料光纖 高壓隔離 通信 接口設(shè)計(jì)
上傳時(shí)間： 2014-01-10
上傳用戶：gundan
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶：wxqman
支持X/Y/Z Modem協(xié)議的傳輸文件的通訊程序
標(biāo)簽： Modem 協(xié)議 傳輸 通訊程序
上傳時(shí)間： 2015-01-03
上傳用戶：xg262122
求N皇后問題回溯算法
標(biāo)簽： 回溯算法
上傳時(shí)間： 2014-07-13
上傳用戶：yph853211
n皇后
標(biāo)簽：
上傳時(shí)間： 2014-02-18
上傳用戶：lili123
N*N的陀螺方陣存入一個(gè)二維數(shù)
上傳時(shí)間： 2013-12-28
上傳用戶：84425894
N*N的陀螺方陣存入一個(gè)二維數(shù)
上傳時(shí)間： 2013-12-27
上傳用戶：zuozuo1215
It is good
上傳時(shí)間： 2014-01-20
上傳用戶：dreamboy36
Arith-N 是可以在命令行指定階數(shù)的 N 階上下文自適應(yīng)算術(shù)編碼通用壓縮、解壓縮程序，由于是用作教程示例，為清晰起見，在某些地方并沒有刻意進(jìn)行效率上的優(yōu)化。由王笨笨大俠提供
標(biāo)簽： Arith-N 命令行 算術(shù)編碼 程序
上傳時(shí)間： 2015-01-08
上傳用戶：bjgaofei
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