Study on High-efficiency and Low-noise Wireless Power Transmission for Solar Power Station/Satellite
標(biāo)簽： Power High-efficiency Transmission Low-noise
上傳時(shí)間： 2014-12-20
上傳用戶：kristycreasy
Study on High-efficiency and Low-noise Wireless Power Transmission for Solar Power Station/Satellite
標(biāo)簽： Power High-efficiency Transmission Low-noise
上傳時(shí)間： 2015-09-24
上傳用戶：teddysha
Study on High-efficiency and Low-noise Wireless Power Transmission for Solar Power Station/Satellite
標(biāo)簽： Power High-efficiency Transmission Low-noise
上傳時(shí)間： 2013-12-19
上傳用戶：zhaiyanzhong
linux virtual server high availability using VRRPv2, keepalive userguide
標(biāo)簽： availability keepalive userguide virtual
上傳時(shí)間： 2014-01-25
上傳用戶：曹云鵬
Interfacing AD7276 High-Speed Data Converters to ADSP-BF535 Blackfin Processors
標(biāo)簽： Interfacing High-Speed Converters Processors
上傳時(shí)間： 2013-12-20
上傳用戶：希醬大魔王
The Staged Event-Driven Architecture (SEDA) is a new design for building scalable Internet services. SEDA has three major goals: To support massive concurrency, on the order of tens of thousands of clients per node To exhibit robust performance under wide variations in load and, To simplify the design of complex Internet services. SEDA decomposes a complex, event-driven application into a set of stages connected by queues. This design avoids the high overhead associated with thread-based concurrency models, and decouples event and thread scheduling from application logic. SEDA enables services to be well-conditioned to load, preventing resources from being overcommitted when demand exceeds service capacity. Decomposing services into a set of stages also enables modularity and code reuse, as well as the development of debugging tools for complex event-driven applications.
標(biāo)簽： Event-Driven Architecture Internet building
上傳時(shí)間： 2015-09-28
上傳用戶：日光微瀾
a high quality statics studying materials, informative and useful
標(biāo)簽： informative materials studying quality
上傳時(shí)間： 2015-10-06
上傳用戶：zwei41
MATLAB implementation of SPIHT (without Arithmatic coding stage). ％ Performance evaluation : this toolbox VS. SPIHT ％ Test image: lena512.raw ％ bpp SPIHT(dB) This code(dB) ％ 0.1000 29.8107 29.3202 ％ 0.2000 32.7202 32.2514 ％ 0.3000 34.5479 34.0331 ％ 0.4000 35.8422 35.4857 ％ 0.5000 36.8623 36.5939 ％ 0.6000 37.6650 37.3759 ％ 0.7000 38.2581 38.0491 ％ 0.8000 38.9390 38.7058 ％ 0.9000 39.5218 39.3437
標(biāo)簽： implementation Performance Arithmatic evaluation
上傳時(shí)間： 2013-12-08
上傳用戶：huannan88
This Document provides the High Level Design specification for the Bootloader development and library porting for ADSP-BF533 based EZ-Kit Lite Board and STAMP Board. This document is meant to be the one of the inputs for the System Test Plan and the overall implementation of the same. This document also details the approach and assumptions made for the design
標(biāo)簽： specification development Bootloader the
上傳時(shí)間： 2015-10-14
上傳用戶：D&L37
一些關(guān)于HLA(high level architecher)仿真程序設(shè)計(jì)的相關(guān)文章,
標(biāo)簽： architecher level high HLA
上傳時(shí)間： 2013-12-19
上傳用戶：邶刖
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