基于ADSP-BF561的數(shù)字?jǐn)z像系統(tǒng)設(shè)計(jì)Design of Digital Video Camera System Based on Digital Signal ProcessorADSP-BF561（浙江大學(xué) 信息與通信工程研究所，浙江 杭州 310027） 馬海杰, 劉云海摘要：介紹了基于ADI雙核的數(shù)字信號(hào)處理芯片ADSP-BF561 的數(shù)字?jǐn)z像系統(tǒng)實(shí)現(xiàn)方案。系統(tǒng)包括硬件和軟件兩部分，硬件主要有ADSP-BF561及其外圍電路、音視頻模數(shù)/數(shù)模轉(zhuǎn)換、CF卡/微硬盤接口等部分。軟件主要有操作系統(tǒng)及音視頻編解碼算法等部分。關(guān)鍵詞：ADSP-BF561 ;數(shù)字?jǐn)z像機(jī);微硬盤;MPEG-4;A/D;D/A中圖分類號(hào):TN948.41文獻(xiàn)標(biāo)識(shí)碼:AAbstract: An implementation of digital video camera system based on ADI dual core digital signal processor ADSP-BF561 is introduced. The system can be divided into two parts——Hardware and software design. The Hardware design includes ADSP-BF561 and perpheral apparatus, A/D,D/A, CF card or Microdrive and so on. The software includes operating system , audio and video coding algorithm.Key words: ADSP-BF561; digital video camera; microdrive; MPEG-4;A/D;D/A
標(biāo)簽： ADSP-BF 561 數(shù)字?jǐn)z像 系統(tǒng)設(shè)計(jì)
上傳時(shí)間： 2013-11-10
上傳用戶：yl1140vista
設(shè)計(jì)一種應(yīng)用于某全地形ATV車載武器裝置中的中控系統(tǒng)，該系統(tǒng)設(shè)計(jì)是以TMS320F2812型DSP為核心，采用模塊化設(shè)計(jì)思想，對(duì)其硬件部分進(jìn)行系統(tǒng)設(shè)計(jì)，能夠完成對(duì)武器裝置高低、回轉(zhuǎn)方向的運(yùn)動(dòng)控制，實(shí)現(xiàn)靜止或行進(jìn)狀態(tài)中對(duì)目標(biāo)物的測(cè)距，自動(dòng)瞄準(zhǔn)以及按既定發(fā)射模式發(fā)射彈丸和各項(xiàng)安全性能檢測(cè)等功能。通過編制相應(yīng)的軟件，對(duì)其進(jìn)行系統(tǒng)調(diào)試，驗(yàn)證了該設(shè)計(jì)運(yùn)行穩(wěn)定。 Abstract: A central control system applied to an ATV vehicle weapons is designed. The system design is based on TMS320F2812 DSP as the core， uses modular design for its Hardware parts. The central control system can complete the motion control of the level of weapons and equipment， rotation direction， to achieve a state of static or moving objects on the target ranging， auto-targeting and according to the established target and the projectile and the launch of the security performance testing and other functions. Through the development of appropriate software and to carry out system testing to verify the stability of this design and operation.
標(biāo)簽： ATV-ATT DSP 中控系統(tǒng)
上傳時(shí)間： 2013-11-02
上傳用戶：jshailingzzh
針對(duì)運(yùn)行中火車測(cè)速運(yùn)用多普勒效應(yīng)采用DSP 設(shè)計(jì)雷達(dá)測(cè)速系統(tǒng)并闡述了其基本設(shè)計(jì)思想與工作原理給出系統(tǒng)硬件軟件設(shè)計(jì)結(jié)構(gòu)和原理圖改善了原有光電測(cè)速精度提高了系統(tǒng)工作穩(wěn)定性和可靠性經(jīng)實(shí)驗(yàn)證明DSP 采集板工作穩(wěn)定測(cè)速效果好關(guān)鍵詞DSP; 雷達(dá)測(cè)速; 多普勒效應(yīng) On Board DSP-Based Radar Speed Measurement System TANG Wei, SUN Zhi-fang, CHEN Quan (Dept.of computer Science,Yangtze University,Jingzhou 434023,China)Abstract: This paper presents a DSP-based train speed measurement by using Doppler radar. The structure of the system is introduced.The Hardware and software are also discussed.Key words: DSP; rader speed measurement; doppler principle
標(biāo)簽： DSP 車載 系統(tǒng)設(shè)計(jì) 雷達(dá)測(cè)速
上傳時(shí)間： 2013-10-27
上傳用戶：003030
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx Hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽： Virtex FPGA PCB 設(shè)計(jì)手冊(cè)
上傳時(shí)間： 2014-01-13
上傳用戶：竺羽翎2222
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and Hardware designers start development simultaneously.
標(biāo)簽： xilinx Zynq 7000 EPP
上傳時(shí)間： 2013-11-01
上傳用戶：dingdingcandy
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx Hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽： CPLD
上傳時(shí)間： 2013-10-22
上傳用戶：李哈哈哈
隨著HDL Hardware Description Language 硬件描述語言語言綜合工具及其它相關(guān)工具的推廣使廣大設(shè)計(jì)工程師從以往煩瑣的畫原理圖連線等工作解脫開來能夠?qū)⒐ぷ髦匦霓D(zhuǎn)移到功能實(shí)現(xiàn)上極大地提高了工作效率任何事務(wù)都是一分為二的有利就有弊我們發(fā)現(xiàn)現(xiàn)在越來越多的工程師不關(guān)心自己的電路實(shí)現(xiàn)形式以為我只要將功能描述正確其它事情交給工具就行了在這種思想影響下工程師在用HDL語言描述電路時(shí)腦袋里沒有任何電路概念或者非常模糊也不清楚自己寫的代碼綜合出來之后是什么樣子映射到芯片中又會(huì)是什么樣子有沒有充分利用到FPGA的一些特殊資源遇到問題立刻想到的是換速度更快容量更大的FPGA器件導(dǎo)致物料成本上升更為要命的是由于不了解器件結(jié)構(gòu)更不了解與器件結(jié)構(gòu)緊密相關(guān)的設(shè)計(jì)技巧過分依賴綜合等工具工具不行自己也就束手無策導(dǎo)致問題遲遲不能解決從而嚴(yán)重影響開發(fā)周期導(dǎo)致開發(fā)成本急劇上升 目前我們的設(shè)計(jì)規(guī)模越來越龐大動(dòng)輒上百萬門幾百萬門的電路屢見不鮮同時(shí)我們所采用的器件工藝越來越先進(jìn)已經(jīng)步入深亞微米時(shí)代而在對(duì)待深亞微米的器件上我們的設(shè)計(jì)方法將不可避免地發(fā)生變化要更多地關(guān)注以前很少關(guān)注的線延時(shí)我相信ASIC設(shè)計(jì)以后也會(huì)如此此時(shí)如果我們不在設(shè)計(jì)方法設(shè)計(jì)技巧上有所提高是無法面對(duì)這些龐大的基于深亞微米技術(shù)的電路設(shè)計(jì)而且現(xiàn)在的競爭越來越激勵(lì)從節(jié)約公司成本角度出 也要求我們盡可能在比較小的器件里完成比較多的功能 本文從澄清一些錯(cuò)誤認(rèn)識(shí)開始從FPGA器件結(jié)構(gòu)出發(fā)以速度路徑延時(shí)大小和面積資源占用率為主題描述在FPGA設(shè)計(jì)過程中應(yīng)當(dāng)注意的問題和可以采用的設(shè)計(jì)技巧本文對(duì)讀者的技能基本要求是熟悉數(shù)字電路基本知識(shí)如加法器計(jì)數(shù)器RAM等熟悉基本的同步電路設(shè)計(jì)方法熟悉HDL語言對(duì)FPGA的結(jié)構(gòu)有所了解對(duì)FPGA設(shè)計(jì)流程比較了解
標(biāo)簽： Xilinx FPGA 華為 高級(jí)技巧
上傳時(shí)間： 2013-11-06
上傳用戶：asdfasdfd
針對(duì)嵌入式機(jī)器視覺系統(tǒng)向獨(dú)立化、智能化發(fā)展的要求，介紹了一種嵌入式視覺系統(tǒng)--智能相機(jī)。基于對(duì)智能相機(jī)體系結(jié)構(gòu)、組成模塊和圖像采集、傳輸和處理技術(shù)的分析，對(duì)國內(nèi)外的幾款智能相機(jī)進(jìn)行比較。綜合技術(shù)發(fā)展現(xiàn)狀，提出基于FPGA+DSP模式的硬件平臺(tái)，并提出智能相機(jī)的發(fā)展方向。分析結(jié)果表明，該系統(tǒng)設(shè)計(jì)可以實(shí)現(xiàn)脫離PC運(yùn)行，完成圖像獲取與分析，并作出相應(yīng)輸出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the Hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.
標(biāo)簽： FPGA DSP 模式 智能相機(jī)
上傳時(shí)間： 2013-10-24
上傳用戶：bvdragon
波長信號(hào)的解調(diào)是實(shí)現(xiàn)光纖光柵傳感網(wǎng)絡(luò)的關(guān)鍵，基于現(xiàn)有的光纖光柵傳感器解調(diào)方法，提出一種基于FPGA的雙匹配光纖光柵解調(diào)方法，此系統(tǒng)是一種高速率、高精度、低成本的解調(diào)系統(tǒng)，并且通過引入雙匹配光柵有效地克服了雙值問題同時(shí)擴(kuò)大了檢測(cè)范圍。分析了光纖光柵的測(cè)溫原理并給出了該方案軟硬件設(shè)計(jì)，綜合考慮系統(tǒng)的解調(diào)精度和FPGA的處理速度給出了基于拉格朗日的曲線擬合算法。 Abstract: Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This paper analyzes the principle of fiber Bragg grating temperature and gives the software and Hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this paper gives the curve fitting algorithm based on Lagrange.
標(biāo)簽： FPGA 光纖光柵 解調(diào)系統(tǒng)
上傳時(shí)間： 2014-07-24
上傳用戶：caiguoqing
本文主要通過介紹PLC通訊的意義和三菱FX系列PLC的四種通訊方式，并重點(diǎn)介紹FX系列PLC與計(jì)算機(jī)無協(xié)議通訊，主要從無協(xié)議通訊的硬件、配線、數(shù)據(jù)寄存器設(shè)置、PLC與計(jì)算機(jī)無協(xié)議通訊的指令用法、PLC程序編寫和計(jì)算機(jī)VB程序的編寫來說明無協(xié)議通訊的過程和一般方法。 My dissertation introduces the significance of PLC communications and the four means of communication of Mitsubishi FX’s PLC, And highlights the no protocol communications of FX series PLC and computer, no protocol communications Hardware, wiring, Register data set, and the usage of command about no protocol communications, How to write PLC program and computer VB program to illustrate the process of no protocol communications and general method.
標(biāo)簽： PLC 三菱FX系列 計(jì)算機(jī) 協(xié)議
上傳時(shí)間： 2014-11-29
上傳用戶：Jerry_Chow
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