The PCA9537 is a 10-pin CMOS device that provides 4 bits of General Purpose parallelInput/Output (GPIO) expansion with interrupt and reset for I2C-bus/SMBus applicationsand was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders.I/O expanders provide a simple solution when additional I/O is needed for ACPI powerswitches, sensors, push-buttons, LEDs, fans, etc.
The PCA9538 is a 16-pin CMOS device that provides 8 bits of General Purpose parallelInput/Output (GPIO) expansion with interrupt and reset for I2C-bus/SMBus applicationsand was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders.I/O expanders provide a simple solution when additional I/O is needed for ACPI powerswitches, sensors, push-buttons, LEDs, fans, etc.
The PCA9539; PCA9539R is a 24-pin CMOS device that provides 16 bits of GeneralPurpose parallel Input/Output (GPIO) expansion with interrupt and reset forI2C-bus/SMBus applications and was developed to enhance the NXP Semiconductorsfamily of I2C-bus I/O expanders. I/O expanders provide a simple solution when additionalI/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallelInput/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed toenhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvementsinclude higher drive capability, 5 V I/O tolerance, lower supply current, individual I/Oconfiguration, and smaller packaging. I/O expanders provide a simple solution whenadditional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Outputand Polarity Inversion (active HIGH or active LOW operation) registers. The systemmaster can enable the I/Os as either inputs or outputs by writing to the I/O configurationbits. The data for each Input or Output is kept in the corresponding Input or Outputregister. The polarity of the read register can be inverted with the Polarity Inversionregister. All registers can be read by the system master. Although pin-to-pin and I2C-busaddress compatible with the PCF8575, software changes are required due to theenhancements, and are discussed in Application Note AN469.
Although Stellaris microcontrollers have generous internal SRAM capabilities, certain applicationsmay have data storage requirements that exceed the 8 KB limit of the Stellaris LM3S8xx seriesdevices. Since microcontrollers do not have an external parallel data-bus, serial memory optionsmust be considered. Until recently, the ubiquitous serial EEPROM/flash device was the only serialmemory solution. The major limitations of EEPROM and flash technology are slow write speed, slowerase times, and limited write/erase endurance.Recently, serial SRAM devices have become available as a solution for high-speed dataapplications. The N256S08xxHDA series of devices, from AMI Semiconductor, offer 32 K x 8 bits oflow-power data storage, a fast Serial Peripheral Interface (SPI) serial bus, and unlimited write cycles.The parts are available in 8-pin SOIC and compact TSSOP packages.
The main oscillator allows either a crystal or single-ended input clock signal. Cost-sensitiveapplications typically use an external crystal with the on-chip oscillator circuit since it is the mostcost-effective solution. It is also possible to use the internal oscillator to clock the device after theboot process has completed.
The CAT9555 is a CMOS device that provides 16-bitparallel input/output port expansion for I²C and SMBuscompatible applications. These I/O expanders providea simple solution in applications where additional I/Osare needed: sensors, power switches, LEDs,pushbuttons, and fans.
The CAT9534 is an 8-bit parallel input/output portexpander for I²C and SMBus compatible applications.These I/O expanders provide a simple solution inapplications where additional I/Os are needed: sensors,power switches, LEDs, pushbuttons, and fans.The CAT9534 consists of an input port register, anoutput port register, a configuration register, a polarityinversion register and an I²C/SMBus-compatible serialinterface.
基于單DSP的VoIP模擬電話適配器研究與實現:提出和實現了一種新穎的基于單個通用數字信號處理器(DSP)的VoIP模擬電話適配器方案。DSP的I/O和存儲資源非常有限，通常適于運算密集型應用，不適宜控制密集型應用[5]。該系統高效利用單DSP的I/O和片內外存儲器資源，采用μC/OS-II嵌入式實時操作系統，支持SIP和TCP-UDP/IP協議，通過LAN或者寬帶接入，使普通電話機成為Internet終端，實現IP電話。該系統軟硬件結構緊湊高效，運行穩定，成本低，具有廣闊的應用前景。關鍵詞：模擬電話適配器；IP電話；數字信號處理器；μC/OS-II
【Abstract】This paper presents a VoIP ATA solution based on a single digital signal processor (DSP). DSPs are suitable for arithmetic-intensiveapplication and unsuitable for control-intensive application because of the limitation of I/O and memory resources. This solution is based on a 16-bitfixed-point DSP and μC/OS-II embedded real-time operating system. It makes good use of the limited resources, supports SIP and TCP-UDP/IPprotocol. It can connect the analog telephone to Internet and realize the VoIP application. This system has a great future for its high efficiency andlow cost.【Key words】Analog telephone adapter (ATA); Voice over Internet protocol (VoIP); Digital signal processor (DSP); μC/OS-II
Research and Implementation of VoIPATA Based on Single DSP
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
