Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determine. Programmable logic devices can be configured in almost an infinitenumber of ways. The same design may fit when you use certain implementation switches, andfail to fit when using other switches. This application note attempts to clarify the CPLd softwareimplementation (CPLdFit) options, as well as discuss implementation tips in CoolRunnerTM-IIdesigns in order to maximize CPLd utilization.
This introduction covers the fundamentals of VHDL as applied to Complex ProgrammableLogic Devices (CPLds). Specifically included are those design practices that translate soundlyto CPLds, permitting designers to use the best features of this powerful language to extractoptimum performance for CPLd designs.
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLd device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
The CoolRunner-II CPLd is a highly uniform family of fast, low-power devices. Theunderlying architecture is a traditional CPLd architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blocks use a PLA configuration that allowsall product terms to be routed and shared among any of the macrocells of the functionblock.
This application note shows how a Xilinx CoolRunnerTM-II CPLd can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can be expanded by the user to perform additional operations usingthe remaining CPLd resources
