Logic2007中文教程 PADS Logic功能，特點(diǎn)及使用教程 本教程描述了PADS Logic 的各種功能和特點(diǎn)、以及使用方法。這些功 能包括： 如何在PADS Logic 中使用工作區(qū)(Working Area)。 如何在PADS Logic 的元件庫(kù)中定義目標(biāo)庫(kù)(Library)。 如何從庫(kù)中搜索有關(guān)的元件(Part)。 如何添加連線(Connection)、總線(Bus)、使用頁(yè)間連接符號(hào) 移動(dòng)(Move)、拷貝(Copy)、刪除(Delete)和編輯(Edit)等操作方式(Mode)。 在設(shè)計(jì)數(shù)據(jù)編輯時(shí)使用查詢/修改(Query/Modify)命令。 如何定義設(shè)計(jì)規(guī)則(Design Rules)。 如何建立網(wǎng)表(Netlist)和SPICE 格式網(wǎng)絡(luò)表以及材料清單(BOM)報(bào)
上傳時(shí)間： 2013-04-24
上傳用戶：zhaoq123
·詳細(xì)說(shuō)明：滑模變結(jié)構(gòu)控制創(chuàng)始人Utkin 經(jīng)典著作 sliding mode control 文件列表: Sliding Mode Control. Utkin .......\Sliding Mode Control. Utkin .......\.......\A-INTRODUCCI郚 E INDICE-SMC.pdf .......\...
標(biāo)簽： Utkin nbsp 滑模變結(jié)構(gòu) 控制
上傳時(shí)間： 2013-06-29
上傳用戶：songrui
This application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, the clock management, the reset control, the boot mode settings and the debug management. It shows how to use the High-density and Medium-density STM32F10xxx product families and describes the minimum hardware resources required to develop an STM32F10xxx application.
上傳時(shí)間： 2013-04-24
上傳用戶：epson850
Abstract: This application note describes how to design boost converters using the MAX17597 peakcurrent-mode controller. Boost converters can be operated in discontinuous conduction mode (DCM) orcontinuous conduction mode (CCM). This operating mode can affect the component choices, stress levelin power devices, and controller design. Formulas for calculating component values and ratingsare alsopresented.
標(biāo)簽： 17597 MAX 如何設(shè)計(jì) 升壓轉(zhuǎn)換器
上傳時(shí)間： 2013-11-16
上傳用戶：zcs023047
交流功率因數(shù)轉(zhuǎn)換器 特點(diǎn)： 精確度0.25%滿刻度 ±0.25o 多種輸入,輸出選擇 輸入與輸出絕緣耐壓2仟伏特/1分鐘 沖擊電壓測(cè)試5仟伏特(1.2x50us) (IEC255-4,ANSI C37.90a/1974) 突波電壓測(cè)試2.5仟伏特(0.25ms/1MHz) (IEC255-4) 尺寸小，穩(wěn)定性高 主要規(guī)格： 精確度: 0.25% F.S. ±0.25°(23 ±5℃) 輸入負(fù)載: <0.2VA (Voltage) <0.2VA (Current) 最大過(guò)載能力: Current related input: 3 x rated continuous 10 x rated 30 sec. 25 x rated 3sec. 50 x rated 1sec. Voltage related input:maximum 2 x rated continuous 輸出反應(yīng)速度: < 250ms(0~90%) 輸出負(fù)載能力: < 10mA for voltage mode < 10V for current mode 輸出之漣波: < 0.1% F.S. 歸零調(diào)整范圍: 0~ ±5% F.S. 最大值調(diào)整范圍: 0~ ±10% F.S. 溫度系數(shù): 100ppm/℃ (0~50℃) 隔離特性: Input/Output/Power/Case 絕緣抗阻: >100Mohm with 500V DC 絕緣耐壓能力: 2KVac/1 min. (input/output/power/case) 突波測(cè)試: ANSI C37.90a/1974,DIN-IEC 255-4 impulse voltage 5KV(1.2x50us) 使用環(huán)境條件: -20~60℃(20 to 90% RH non-condensed) 存放環(huán)境條件: -30~70℃(20 to 90% RH non-condensed) CE認(rèn)證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
標(biāo)簽： 交流 功率因數(shù)轉(zhuǎn)換器
上傳時(shí)間： 2013-10-22
上傳用戶：thing20
交流頻率轉(zhuǎn)換器 特點(diǎn)： 精確度0.05%滿刻度(Accuracy 0.05%F.S.) 多種輸入,輸出選擇 輸入與輸出絕緣耐壓2仟伏特/1分鐘 沖擊電壓測(cè)試5仟伏特(1.2x50us) (IEC255-4,ANSI C37.90a/1974) 突波電壓測(cè)試2.5仟伏特(0.25ms/1MHz) (IEC255-4) 尺寸小，穩(wěn)定性高 2:主要規(guī)格 精確度: 0.05% F.S. (23 ±5℃) 輸入負(fù)載: <0.2VA 最大過(guò)載能力:maximum 2 x rated continuous 輸出反應(yīng)時(shí)間: <250ms (0~90%) 輸出負(fù)載能力: <10mA for voltage mode <10V for current mode 輸出漣波: <0.1% F.S. 歸零調(diào)整范圍: 0~±5% F.S. 最大值調(diào)整范圍: 0~±10% F.S. 溫度系數(shù): 50ppm/℃ (0~50℃) 隔離特性: Input/Output/Power/Case 絕緣抗阻: >100M ohm with 500V DC 絕緣耐壓能力: 2KVac/1 min. (input/output/power) 行動(dòng)測(cè)試: ANSI C37.90a/1974,DIN-IEC 255-4 impulse voltage 5KV (1.2 x 50us) 突波測(cè)試: 2.5KV-0.25ms/1MHz 使用環(huán)境條件: -20~60℃(20 to 90% RH non-condensed) 存放環(huán)境條件: -30~70℃(20 to 90% RH non-condensed) CE認(rèn)證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
標(biāo)簽： 交流 頻率轉(zhuǎn)換器
上傳時(shí)間： 2013-10-11
上傳用戶：xzt
交流電壓，電流轉(zhuǎn)換器 特點(diǎn)： 精確度0.25%滿刻度(RMS) 多種輸入,輸出選擇 輸入與輸出絕緣耐壓2仟伏特/1分鐘 沖擊電壓測(cè)試5仟伏特(1.2x50us) (IEC255-4,ANSI C37.90a/1974) 突波電壓測(cè)試2.5仟伏特(0.25ms/1MHz) (IEC255-4) 尺寸小，穩(wěn)定性高 2:主要規(guī)格 精確度:0.25%F.S.(RMS) (23 ±5℃) 輸入負(fù)載: <0.2VA(voltage) <0.2VA(current) 最大過(guò)載能力: Current related input:3 x rated continuous 10 x rated 30 sec. ,25 x rated 3sec. 50 x rated 1sec. Voltage related input:maximum 2x rated continuous 輸出反應(yīng)時(shí)間: <250ms (0~90%) 輸出負(fù)載能力: <10mA for voltage mode <10V for current mode 輸出漣波: <0.1% F.S. 歸零調(diào)整范圍: 0~±5% F.S. 最大值調(diào)整范圍: 0~±10% F.S. 溫度系數(shù): 100ppm/℃ (0~50℃) 隔離特性: Input/Output/Power/Case 絕緣抗阻: >100Mohm with 500V DC 絕緣耐壓能力: 2KVac/1 min. (input/output/power) 行動(dòng)測(cè)試: ANSI C37.90a/1974,DIN-IEC 255-4 impulse voltage 5KV (1.2 x 50us) 突波測(cè)試: 2.5KV-0.25ms/1MHz 使用環(huán)境條件: -20~60℃(20 to 90% RH non-condensed) 存放環(huán)境條件: -30~70℃(20 to 90% RH non-condensed) CE認(rèn)證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
標(biāo)簽： 交流電壓 電流轉(zhuǎn)換器
上傳時(shí)間： 2013-11-09
上傳用戶：非衣2016
Abstract: Alexander Graham Bell patented twisted pair wires in 1881. We still use them today because they work so well. In addition we have the advantage ofincredible computer power within our world. Circuit simulators and filter design programs are available for little or no cost. We combine the twisted pair and lowpassfilters to produce spectacular rejection of radio frequency interference (RFI) and electromagnetic interference (EMI). We also illustrate use of a precision resistorarray to produce a customizable differential amplifier. The precision resistors set the gain and common mode rejection ratios, while we choose the frequencyresponse.
上傳時(shí)間： 2014-11-26
上傳用戶：Vici
采用電流模脈寬調(diào)制控制方案的電池充電芯片設(shè)計(jì),鋸齒波信號(hào)的線性度較好,當(dāng)負(fù)載電路減小時(shí),自動(dòng)進(jìn)入Burst Mode狀態(tài)提高系統(tǒng)的效率。整個(gè)電路基于1.0 μm 40 V CMOS工藝設(shè)計(jì),通過(guò)Hspice完成了整體電路前仿真驗(yàn)證和后仿真,仿真結(jié)果表明,振蕩電路的性能較好,可廣泛應(yīng)用在PWM等各種電子電路中。
上傳時(shí)間： 2014-12-23
上傳用戶：kangqiaoyibie
A fully differential amplifi er is often used to converta single-ended signal to a differential signal, a designwhich requires three signifi cant considerations: theimpedance of the single-ended source must match thesingle-ended impedance of the differential amplifi er,the amplifi er’s inputs must remain within the commonmode voltage limits and the input signal must be levelshifted to a signal that is centered at the desired outputcommon mode voltage.
上傳時(shí)間： 2013-11-09
上傳用戶：wweqas
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
