This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on Both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上傳時間： 2013-10-15
上傳用戶：busterman
Abstract: There are many things to consider when designing a power supply for a field-programmablegate array (FPGA). These include (but are not limited to) the high number of voltage rails, and thediffering requirements for Both sequencing/tracking and the voltage ripple limits. This application noteexplains these and other power-supply considerations that an engineer must think through whendesigning a power supply for an FPGA.
上傳時間： 2013-11-12
上傳用戶：金苑科技
While simplicity and high effi ciency (for cool running) areno longer optional features in isolated power supplies, itis traditionally diffi cult to achieve Both. Achieving higheffi ciency often requires the use of advanced topologiesand home-brewed secondary synchronous rectifi cationschemes once reserved only for higher power applications.This only adds to the parts count and to the designcomplexity associated with the reference and optocouplercircuits typically used to maintain isolation. Fortunately, abreakthrough IC makes it possible to achieve Both high efficiency and simplicity in a synchronous fl yback topology.The LT®3825 simplifi es and improves the performance oflow voltage, high current fl yback supplies by providingprecise synchronous rectifi er timing and eliminating theneed for optocoupler feedback while maintaining excellentregulation and superior loop response.
上傳時間： 2013-10-16
上傳用戶：wayne595
Automotive batteries, industrial power supplies, distributedsupplies and wall transformers are all sources ofwide-ranging high voltage inputs. The easiest way to stepdown these sources is with a high voltage monolithicstep-down regulator that can directly accept a wide inputrange and produce a well-regulated output. The LT®3493accepts inputs from 3.6V to 36V and LT3481 acceptsinputs from 3.6V to 34V. Both provide excellent lineand load regulation and dynamic response. The LT3481offers a high effi ciency solution over a wide load range andkeeps the output ripple low during Burst Mode® operationwhile the LT3493 provides a tiny solution with minimalexternal components. The LT3493 operates at 750kHzand the LT3481 has adjustable frequency from 300kHzto 2.8MHz. High frequency operation enables the use ofsmall, low cost inductors and ceramic capacitors.
標簽： 寬 輸入 降壓型穩(wěn)壓器
上傳時間： 2014-12-24
上傳用戶：Pzj
Piezoelectric motors are used in digital cameras for autofocus,zooming and optical image stabilization. Theyare relatively small, lightweight and effi cient, but theyalso require a complicated driving scheme. Traditionally,this challenge has been met with the use ofseparatecircuits, including a step-up converter and an oversizedgeneric full-bridge drive IC. The resulting high componentcount and large board space are especially problematicin the design of cameras for ever shrinking cell phones.The LT®3572 solves these problems by combining astep-up regulator and a dual full-bridge driver in a 4mm× 4mm QFN package. Figure 1 shows a typical LT3572Piezo motor drive circuit. A step-up converter is usedto generate 30V from a low voltage power source suchas a Li-Ion battery or any input power source within thepart’s wide input voltage range of 2.7V to 10V. The highoutput voltage of the step-up converter, adjustable upto 40V, is available for the drivers at the VOUT pin. Thedrivers operate in a full-bridge fashion, where the OUTAand OUTB pins are the same polarity as the PWMA andPWMB pins, respectively, and the OUTA and OUTB pinsare inverted from PWMA and PWMB, respectively. Thestep-up converter and Both Piezo drivers have their ownshutdown control. Figure 2 shows a typical layout
上傳時間： 2013-11-18
上傳用戶：hulee
In an increasing trend, telecommunications, networking,audio and instrumentation require low noise power supplies.In particular, there is interest in low noise, lowdropout linear regulators (LDO). These components powernoise-sensitive circuitry, circuitry that contains noisesensitiveelements or Both. Additionally, to conserve power,particularly in battery driven apparatus such as cellulartelephones, the regulators must operate with low input-tooutputvoltages.1 Devices presently becoming availablemeet these requirements (see separate section, “A Familyof 20mVRMS Noise, Low Dropout Regulators”).
標簽： 低噪聲 低壓差穩(wěn)壓器 性能
上傳時間： 2013-10-30
上傳用戶：yeling1919
The latest generation of Texas Instruments (TI) boardmountedpower modules utilizes a pin interconnect technologythat improves surface-mount manufacturability.These modules are produced as a double-sided surfacemount(DSSMT) subassembly, yielding a case-less constructionwith subcomponents located on Both sides of theprinted circuit board (PCB). Products produced in theDSSMT outline use the latest high-efficiency topologiesand magnetic-component packaging. This providescustomers with a high-efficiency, ready-to-use switchingpower module in a compact, space-saving package. Bothnonisolated point-of-load (POL) switching regulators andthe isolated dc/dc converter modules are being producedin the DSSMT outline.TI’s plug-in power product line offers power modules inBoth through-hole and surface-mount packages. The surfacemountmodules produced in the DSSMT outline use asolid copper interconnect with an integral solder ball fortheir
上傳時間： 2013-10-10
上傳用戶：1184599859
Abstract: This application note describes how to build, debug, and run applications on the on-board MAXQ622microcontroller to interface with the DS8005 dual smart card interface. This is demonstrated in Both IAREmbedded Workbench and the Rowley CrossWorks IDE, using sample code provided with the kit.
上傳時間： 2013-10-29
上傳用戶：ddddddd
The MAX9257/MAX9258 programmable serializer/deserializer (SerDes) devices transfer Both video data and control signals over the same twisted-pair cable. However, control data can only be transmitted during the vertical blank time, which is indicated by the control-channel-enabled output (CCEN) signal. The electronic control unit (ECU) firmware designer needs to know how quickly to respond to the CCEN signal before it times out and how to calculate this duration. This application note describes how to calculate the duration of the CCEN for the MAX9257/MAX9258 SerDes chipset. The calculation is based on STO timeout, clock frequency, and UART bit timing. The CCEN duration is programmable and can be closed if not in use.
上傳時間： 2014-01-24
上傳用戶：xingisme
在航電系統(tǒng)維護過程中，為解決定位故障的效率和降低維修成本等問題，提出了基于ICD（Interface Control Document，接口控制文件）的1553B總線的信息監(jiān)控系統(tǒng)模型。該系統(tǒng)運用數(shù)據(jù)采集卡對總線中傳輸?shù)男盘栍袩o失真、偏差等電氣特性進行檢測，并使用1553B通訊卡通過測控軟件LabWindows/CVI編程與ICD數(shù)據(jù)庫的動態(tài)鏈接，實現(xiàn)總線信息的解析和故障的判斷。與傳統(tǒng)的維護過程相比，這種模型能夠從信號的電氣特性以及信息的解析等全方位的去檢測判斷故障的來源，并且能夠廣泛在其他1553B總線系統(tǒng)內(nèi)擴展應用。驗證表明該監(jiān)控系統(tǒng)可以對總線信息進行快速有效地監(jiān)測分析，能滿足應用需求。 Abstract: In the process of avionics system maintenance， to solve the problems such as improving the efficiency of fast orientation to troubles and reducing maintenance cost， system of 1553B bus information monitor model based on ICD was proposed. The system observed whether the data which transmitted on the bus appear distortion and deviation by using data acquisition card. And using 1553B communication card programming of the measure software LabWindows/CVI and the dynamic linking of ICD database， message analysis and fault estimation could be realized. Compared with traditional maintenance， this model can all-dimensionally detect and analyze the source of faults from Both electrical characteristics of the signal and message analysis， and it can be widely applied in the other 1553B system. Experiment shown that this monitor system can effectively detect and analyze the bus message and can meet the application requirements.
標簽： 1553B 總線 信息監(jiān)控
上傳時間： 2013-11-23
上傳用戶：18752787361
