The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
上傳時間： 2014-12-30
上傳用戶：aysyzxzm
Abstract: This application note discusses a design for a phantom antenna power-supply system compatible with theDigital Satellite Equipment Control (DiSEqC) communication standard, using the MAX16948 automotive dual, highvoltageLDO/switch. The presented application circuit provides a remote antenna power supply and also enables onewaycommunication from the radio head unit to the remote antenna. This system architecture offers flexibility inDiSEqC tone-burst frequency choice (100Hz to 30kHz), enabling users the ability to select the best frequency for theirapplication.
上傳時間： 2013-11-17
上傳用戶：fnhhs
目錄 一、Smart Phone Market Share 1.1、中國智能手機銷售量與變化狀況 1.2、智能手機操作系統份額走勢 1.3、智能手機銷售價格走勢 二、展訊智能手機方案 三、TI 無線充電方案 四、Freescale G+M二合一 Sensor 五、NXP NFC 六、TI 五合一 無線芯片 展訊智能手機方案框圖
上傳時間： 2014-12-30
上傳用戶：blacklee
Abstract: While many questions still surround the creation and deployment of the smart grid, the need for a reliablecommunications infrastructure is indisputable. Developers of the IEEE 1901.2 standard identified difficult channel conditionscharacteristic of low-frequency powerline communications and implemented an orthogonal frequency division multiplexing (OFDM)architecture using advanced modulation and channel-coding techniques. This strategy helped to ensure a robust communicationsnetwork for the smart grid.
上傳時間： 2013-10-18
上傳用戶：myworkpost
在研究傳統家用燃氣報警器的基礎上，以ZigBee協議為平臺，構建mesh網狀網絡實現網絡化的智能語音報警系統。由于傳感器本身的溫度和實際環境溫度的影響，傳感器標定后采用軟件補償方法。為了減少系統費用，前端節點采用半功能節點設備，路由器和協調器采用全功能節點設備，構建mesh網絡所形成的家庭內部報警系統，通過通用的電話接口連接到外部的公用電話網絡，啟動語音模塊進行報警。實驗結果表明，在2.4 GHz頻率下傳輸，有墻等障礙物的情況下，節點的傳輸距離大約為35 m，能夠滿足家庭需要，且系統工作穩定，但在功耗方面仍需進一步改善。 Abstract: On the basis of studying traditional household gas alarm system, this paper proposed the platform for the ZigBee protocol，and constructed mesh network to achieve network-based intelligent voice alarm system. Because of the sensor temperature and the actual environment temperature, this system design used software compensation after calibrating sensor. In order to reduce system cost, semi-functional node devices were used as front-end node, however, full-function devices were used as routers and coordinator，constructed alarm system within the family by building mesh network，connected to the external public telephone network through the common telephone interface, started the voice alarm module. The results indicate that nodes transmit about 35m in the distance in case of walls and other obstacles by 2.4GHz frequency transmission, this is able to meet family needs and work steadily, but still needs further improvement in power consumption.
上傳時間： 2013-10-30
上傳用戶：swaylong
為了能夠滿足基站易于選址、優質快速的建站要求和易維護、低成本、高可靠的運行要求，本文對以方艙來實現一體化結構基站做出一番探討。從系統設計的觀點闡述了移動通信高性能基站天線設計的幾個關鍵問題，介紹了智能天線技術在基站中的應用，并且用HFSS軟件仿真了一種新型的對稱陣子天線，該天線駐波比小于2的帶寬可以達到60%，具有良好的寬頻帶特性。 Abstract: In order to meet the station construction requirement of easy site selection and fast base station， and meet the operational requirement of easy maintenance， low cost and high reliability， this paper discussed the unified architecture base station using shelter. Several key problems of high performance mobile communication base station antenna were illustrated from the view of system design， the application of smart antenna in base station was also introduced. And a novel dipole antenna was simulated by using HFSS， the VSWR of the antenna is less than 2， and the bandwidth was reach to 60%. So it has good broadband properties.
上傳時間： 2013-11-20
上傳用戶：linlin
為滿足無線網絡技術具有低功耗、節點體積小、網絡容量大、網絡傳輸可靠等技術要求，設計了一種以MSP430單片機和CC2420射頻收發器組成的無線傳感節點。通過分析其節點組成，提出了ZigBee技術中的幾種網絡拓撲形式，并研究了ZigBee路由算法。針對不同的傳輸要求形式選用不同的網絡拓撲形式可以盡大可能地減少系統成本。同時針對不同網絡選用正確的ZigBee路由算法有效地減少了網絡能量消耗，提高了系統的可靠性。應用試驗表明，采用ZigBee方式通信可以提高傳輸速率且覆蓋范圍大，與傳統的有線通信方式相比可以節約40%左右的成本。 Abstract: To improve the proposed technical requirements such as low-ower， small nodes， large capacity and reliable network transmission， wireless sensor nodes based on MSP430 MCU and CC2420 RF transceiver were designed. This paper provided network topology of ZigBee technology by analysing the component of the nodes and researched ZigBee routing algorithm. Aiming at different requirements of transmission mode to choose the different network topologies form can most likely reduce the system cost. And aiming at different network to choose the correct ZigBee routing algorithm can effectively reduced the network energy consumption and improved the reliability of the system. Results show that the communication which used ZigBee mode can improve the transmission rate， cover more area and reduce 40% cost compared with traditional wired communications mode.
上傳時間： 2013-10-09
上傳用戶：robter
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.
上傳時間： 2014-12-31
上傳用戶：zhuoying119
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上傳時間： 2013-10-28
上傳用戶：15501536189
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
