We have a group of N items (represented by integers from 1 to N), and we know that there is some total order defined for these items. You may assume that no two elements will be equal (for all a, b: a<b or b<a). However, it is expensive to compare two items. Your task is to make a number of comparisons, and then output the sorted order. The cost of determining if a < b is given by the bth integer of element a of costs (space delimited), which is the same as the ath integer of element b. Naturally, you will be judged on the total cost of the comparisons you make before outputting the sorted order. If your order is incorrect, you will receive a 0. Otherwise, your score will be opt/cost, where opt is the best cost anyone has achieved and cost is the total cost of the comparisons you make (so your score for a test case will be between 0 and 1). Your score for the problem will simply be the sum of your scores for the individual test cases.
標(biāo)簽： represented integers group items
上傳時(shí)間： 2016-01-17
上傳用戶：jeffery
嵌入式程序，實(shí)現(xiàn)了在altera FPGA DE2上面的 micro/us 實(shí)時(shí)操作系統(tǒng)，幾個(gè)任務(wù)間的互相轉(zhuǎn)換，以及時(shí)間的控制。
標(biāo)簽： 嵌入式程序
上傳時(shí)間： 2013-12-19
上傳用戶：13188549192
hdb3的發(fā)送端源代碼，采用verilog可綜合格式書寫。已經(jīng)在多款fpga和cpld芯片成功綜合實(shí)現(xiàn)。
上傳時(shí)間： 2013-12-26
上傳用戶：924484786
The XML Toolbox converts MATLAB data types (such as double, char, struct, complex, sparse, logical) of any level of nesting to XML format and vice versa. For example, >> project.name = MyProject >> project.id = 1234 >> project.param.a = 3.1415 >> project.param.b = 42 becomes with str=xml_format(project, off ) "<project> <name>MyProject</name> <id>1234</id> <param> <a>3.1415</a> <b>42</b> </param> </project>" On the other hand, if an XML string XStr is given, this can be converted easily to a MATLAB data type or structure V with the command V=xml_parse(XStr).
標(biāo)簽： converts Toolbox complex logical
上傳時(shí)間： 2016-02-12
上傳用戶：a673761058
采用Verilog HDL語言編寫的多功能數(shù)字鐘，包括四個(gè)功能：時(shí)間顯示與設(shè)置、秒表、鬧鐘、日期顯示與設(shè)置，源代碼對FPGA和CPLD學(xué)習(xí)者價(jià)值很高，
上傳時(shí)間： 2016-03-21
上傳用戶：270189020
VHDL書寫VGA源碼，可用于FPGA和CPLD
上傳時(shí)間： 2016-05-23
上傳用戶：xwd2010
：介紹一種僅使用配置空間設(shè)計(jì)PCI板卡的方法，使扳卡設(shè)計(jì)者能比較客易從ISA過渡到 PCI設(shè)計(jì)，該方法基于FPGA／CPLD，在最小設(shè)計(jì)模式下，僅使用18個(gè)引腳就能實(shí)現(xiàn)簡易的眥功能 卡。
上傳時(shí)間： 2014-01-15
上傳用戶：鳳臨西北
SD card controller can just read data using 1 bit SD mode. I have written this core for NIOS2 CPU, Cyclone, but I think it can works with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and CPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core. Good luck
標(biāo)簽： controller written NIOS2 using
上傳時(shí)間： 2016-08-12
上傳用戶：王楚楚
QuartusII簡介手冊+中文版 本手冊針對的讀者是 Quartus II 軟件的初學(xué)者，它概述了可編程邏輯設(shè)計(jì)中 Quartus II 軟件的功能。 不過，本手冊并不是 Quartus II 軟件的詳盡參考手 冊。 相反，本手冊只是一本指導(dǎo)書，它解釋軟件的功能以及顯示這些功能如 何幫助您進(jìn)行 FPGA 和 CPLD 設(shè)計(jì)。
標(biāo)簽： QuartusII Quartus II
上傳時(shí)間： 2013-12-21
上傳用戶：hj_18
一個(gè)FIFO源代碼，基于Altera FPGA
上傳時(shí)間： 2014-01-24
上傳用戶：王者A
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