中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
There has long been a need for portable ultrasoundsystems that have good resolution at affordable costpoints. Portable systems enable healthcare providersto use ultrasound in remote locations such asdisaster zones, developing regions, and battlefields,where it was not previously practical to do so.
上傳時間： 2013-10-26
上傳用戶：liulinshan2010
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
上傳時間： 2013-11-05
上傳用戶：維子哥哥
Design techniques for electronic systems areconstantly changing. In industries at the heart of thedigital revolution, this change is especially acute.Functional integration, dramatic increases incomplexity, new standards and protocols, costconstraints, and increased time-to-market pressureshave bolstered both the design challenges and theopportunities to develop modern electronic systems.One trend driving these changes is the increasedintegration of core logic with previously discretefunctions to achieve higher performance and morecompact board designs.
上傳時間： 2014-12-28
上傳用戶：康郎
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
上傳時間： 2013-11-01
上傳用戶：dingdingcandy
XAPP520將符合2.5V和3.3V I/O標準的7系列FPGA高性能I/O Bank進行連接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上傳時間： 2013-11-19
上傳用戶：yyyyyyyyyy
針對嵌入式機器視覺系統向獨立化、智能化發展的要求，介紹了一種嵌入式視覺系統--智能相機?；趯χ悄芟鄼C體系結構、組成模塊和圖像采集、傳輸和處理技術的分析，對國內外的幾款智能相機進行比較。綜合技術發展現狀，提出基于FPGA+DSP模式的硬件平臺，并提出智能相機的發展方向。分析結果表明，該系統設計可以實現脫離PC運行，完成圖像獲取與分析，并作出相應輸出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.
上傳時間： 2013-10-24
上傳用戶：bvdragon
Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anactive member of the VSIA Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.
上傳時間： 2014-01-24
上傳用戶：xinhaoshan2016
a8259 可編程中斷控制 altera提供 The a8259 is designed to simplify the implementation of the interrupt interface in 8088 and 8086 based microcomputer systems. The device is known as a programmable interrupt controller. The a8259 receives and prioritizes up to 8 interrupts, and in the cascade mode, this can be expanded up to 64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.
上傳時間： 2014-11-29
上傳用戶：zhyiroy
很多不同的廠家生產各種型號的計算機，它們運行完全不同的操作系統，但TCP.IP協議族允許它們互相進行通信。這一點很讓人感到吃驚，因為它的作用已遠遠超出了起初的設想。T C P / I P起源于6 0年代末美國政府資助的一個分組交換網絡研究項目，到9 0年代已發展成為計算機之間最常應用的組網形式。它是一個真正的開放系統，因為協議族的定義及其多種實現可以不用花錢或花很少的錢就可以公開地得到。它成為被稱作“全球互聯網”或“因特網(Internet)”的基礎，該廣域網（WA N）已包含超過1 0 0萬臺遍布世界各地的計算機。本章主要對T C P / I P協議族進行概述，其目的是為本書其余章節提供充分的背景知識。 TCP.IP協議 縮略語 ACK (ACKnowledgment) TCP首部中的確認標志 API (Application Programming Interface) 應用編程接口 ARP (Address Resolution Protocol) 地址解析協議 ARPANET(Defense Advanced Research Project Agency NETwork) (美國)國防部遠景研究規劃局 AS (Autonomous System) 自治系統 ASCII (American Standard Code for Information Interchange) 美國信息交換標準碼 ASN.1 (Abstract Syntax Notation One) 抽象語法記法1 BER (Basic Encoding Rule) 基本編碼規則 BGP (Border Gateway Protocol) 邊界網關協議 BIND (Berkeley Internet Name Domain) 伯克利I n t e r n e t域名 BOOTP (BOOTstrap Protocol) 引導程序協議 BPF (BSD Packet Filter) BSD 分組過濾器 CIDR (Classless InterDomain Routing) 無類型域間選路 CIX (Commercial Internet Exchange) 商業互聯網交換 CLNP (ConnectionLess Network Protocol) 無連接網絡協議 CRC (Cyclic Redundancy Check) 循環冗余檢驗 CSLIP (Compressed SLIP) 壓縮的S L I P CSMA (Carrier Sense Multiple Access) 載波偵聽多路存取 DCE (Data Circuit-terminating Equipment) 數據電路端接設備 DDN (Defense Data Network) 國防數據網 DF (Don’t Fragment) IP首部中的不分片標志 DHCP (Dynamic Host Configuration Protocol) 動態主機配置協議 DLPI (Data Link Provider Interface) 數據鏈路提供者接口 DNS (Domain Name System) 域名系統 DSAP (Destination Service Access Point) 目的服務訪問點 DSLAM (DSL Access Multiplexer) 數字用戶線接入復用器 DSSS (Direct Sequence Spread Spectrum) 直接序列擴頻 DTS (Distributed Time Service) 分布式時間服務 DVMRP (Distance Vector Multicast Routing Protocol) 距離向量多播選路協議 EBONE (European IP BackbONE) 歐洲I P主干網 EOL (End of Option List) 選項清單結束 EGP (External Gateway Protocol) 外部網關協議 EIA (Electronic Industries Association) 美國電子工業協會 FCS (Frame Check Sequence) 幀檢驗序列 FDDI (Fiber Distributed Data Interface) 光纖分布式數據接口 FIFO (First In, First Out) 先進先出 FIN (FINish) TCP首部中的結束標志 FQDN (Full Qualified Domain Name) 完全合格的域名 FTP (File Transfer Protocol) 文件傳送協議 HDLC (High-level Data Link Control) 高級數據鏈路控制 HELLO 選路協議 IAB (Internet Architecture Board) Internet體系結構委員會 IANA (Internet Assigned Numbers Authority) Internet號分配機構 ICMP (Internet Control Message Protocol) Internet控制報文協議 IDRP (InterDomain Routing Protocol) 域間選路協議 IEEE (Institute of Electrical and Electronics Engineering) （美國）電氣與電子工程師協會 IEN (Internet Experiment Notes) 互聯網試驗注釋 IESG (Internet Engineering Steering Group) Internet工程指導小組 IETF (Internet Engineering Task Force) Internet工程專門小組 IGMP (Internet Group Management Protocol) Internet組管理協議 IGP (Interior Gateway Protocol) 內部網關協議 IMAP (Internet Message Access Protocol) Internet報文存取協議 IP (Internet Protocol) 網際協議 I RTF (Internet Research Task Force) Internet研究專門小組 IS-IS (Intermediate System to Intermediate System Protocol) 中間系統到中間系統協議 ISN (Initial Sequence Number) 初始序號 ISO (International Organization for Standardization) 國際標準化組織 ISOC (Internet SOCiety) Internet協會 LAN (Local Area Network) 局域網 LBX (Low Bandwidth X) 低帶寬X LCP (Link Control Protocol) 鏈路控制協議 LFN (Long Fat Net) 長肥網絡 LIFO (Last In, First Out) 后進先出 LLC (Logical Link Control) 邏輯鏈路控制 LSRR (Loose Source and Record Route) 寬松的源站及記錄路由 MBONE (Multicast Backbone On the InterNEt) Internet上的多播主干網 MIB (Management Information Base) 管理信息庫 MILNET (MILitary NETwork) 軍用網 MIME (Multipurpose Internet Mail Extensions) 通用I n t e r n e t郵件擴充 MSL (Maximum Segment Lifetime) 報文段最大生存時間 MSS (Maximum Segment Size) 最大報文段長度 M TA (Message Transfer Agent) 報文傳送代理 MTU (Maximum Transmission Unit) 最大傳輸單元 NCP (Network Control Protocol) 網絡控制協議 NFS (Network File System) 網絡文件系統 NIC (Network Information Center) 網絡信息中心 NIT (Network Interface Tap) 網絡接口栓（S u n公司的一個程序） NNTP (Network News Transfer Protocol) 網絡新聞傳送協議 NOAO (National Optical Astronomy Observatories) 國家光學天文臺 NOP (No Operation) 無操作 NSFNET (National Science Foundation NETwork) 國家科學基金網絡 NSI (NASA Science Internet) （美國）國家宇航局I n t e r n e t NTP (Network Time Protocol) 網絡時間協議 NVT (Network Virtual Terminal) 網絡虛擬終端 OSF (Open Software Foudation) 開放軟件基金 OSI (Open Systems Interconnection) 開放系統互連 OSPF (Open Shortest Path First) 開放最短通路優先 PAWS (Protection Against Wrapped Sequence number) 防止回繞的序號 PDU (Protocol Data Unit) 協議數據單元 POSIX (Portable Operating System Interface) 可移植操作系統接口 PPP (Point-to-Point Protocol) 點對點協議 PSH (PuSH) TCP首部中的急迫標志 RARP (Reverse Address Resolution Protocol) 逆地址解析協議 RFC (Request For Comments) Internet的文檔，其中的少部分成為標準文檔 RIP (Routing Information Protocol) 路由信息協議 RPC (Remote Procedure Call) 遠程過程調用 RR (Resource Record) 資源記錄 RST (ReSeT) TCP首部中的復位標志 RTO (Retransmission Time Out) 重傳超時 RTT (Round-Trip Time) 往返時間 SACK (Selective ACKnowledgment) 有選擇的確認 SLIP (Serial Line Internet Protocol) 串行線路I n t e r n e t協議 SMI (Structure of Management Information) 管理信息結構 SMTP (Simple Mail Transfer Protocol) 簡單郵件傳送協議 SNMP (Simple Network Management Protocol) 簡單網絡管理協議 SSAP (Source Service Access Point) 源服務訪問點 SSRR (Strict Source and Record Route) 嚴格的源站及記錄路由 SWS (Silly Window Syndrome) 糊涂窗口綜合癥 SYN (SYNchronous) TCP首部中的同步序號標志 TCP (Transmission Control Protocol) 傳輸控制協議 TFTP (Trivial File Transfer Protocol) 簡單文件傳送協議 TLI (Transport Layer Interface) 運輸層接口 TTL (Ti m e - To-Live) 生存時間或壽命 TUBA (TCP and UDP with Bigger Addresses) 具有更長地址的T C P和U D P Telnet 遠程終端協議 UA (User Agent) 用戶代理 UDP (User Datagram Protocol) 用戶數據報協議 URG (URGent) TCP首部中的緊急指針標志 UTC (Coordinated Universal Time) 協調的統一時間 UUCP (Unix-to-Unix CoPy) Unix到U n i x的復制 WAN (Wide Area Network) 廣域網 WWW (World Wide Web) 萬維網 XDR (eXternal Data Representation) 外部數據表示 XID (transaction ID) 事務標識符 XTI (X/Open Transport Layer Interface) X/ O p e n運輸層接口
上傳時間： 2013-11-13
上傳用戶：tdyoung
