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• design electronic clock by DS12887, file hex免費下載

  資源簡介：design electronic clock by DS12887, file hex

  標簽： electronic design clock 12887

  上傳時間： 2013-12-19

  上傳用戶：wangdean1101

• fpga design 2 by zip file免費下載

  資源簡介：fpga design 2 by zip file

  標簽： design fpga file zip

  上傳時間： 2017-08-18

  上傳用戶：星仔

• fpage design 3 by zip file免費下載

  資源簡介：fpage design 3 by zip file

  標簽： design fpage file zip

  上傳時間： 2017-08-18

  上傳用戶：佳期如夢

• Java/J2EE application framework based on [Expert One-on-One J2EE design and Development] by Rod John免費下載

  資源簡介：Java/J2EE application framework based on [Expert One-on-One J2EE design and Development] by Rod Johnson. Includes JavaBeans-based configuration, an AOP framework, declarative transaction management, JDBC and Hibernate support, and a web MVC...

  標簽： Development application One-on-One framework

  上傳時間： 2014-01-09

  上傳用戶：saharawalker

• It is a source code for access and program from PIC 18F452 to DS1307 Real Time clock by I2C interfac免費下載

  資源簡介：It is a source code for access and program from PIC 18F452 to DS1307 Real Time clock by I2C interface using I2C capability of microcontroller

  標簽： interfac program 18F452 access

  上傳時間： 2017-04-21

  上傳用戶：lanjisu111

• circuit design with vhdl by pedroni免費下載

  資源簡介：circuit design with vhdl by pedroni

  標簽： circuit pedroni design with

  上傳時間： 2014-12-07

  上傳用戶：jjj0202

• ASIC design using VHDL by Shyam Mani免費下載

  資源簡介：ASIC design using VHDL by Shyam Mani

  標簽： design using Shyam ASIC

  上傳時間： 2017-06-24

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• 基于AVR單片機Mega16的電子時鐘設計免費下載

  資源簡介：Mega16是一款采用先進RISC精簡指令，內置A/D的8位單片機，可支持低電壓聯機 Flash和EEPROM 寫入功能；同時還支持 Basic和C 等高級語言編程。用它設計電子時鐘不僅成本低，硬件簡單，而且很容易實現系統(tǒng)移植。介紹了如何利用AVR系列單片機Mega16及1602字符液晶...

  標簽： Mega AVR 16 單片機

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• 基于Verilog HDL設計的多功能數字鐘免費下載

  資源簡介：本文利用Verilog HDL 語言自頂向下的設計方法設計多功能數字鐘，突出了其作為硬件描述語言的良好的可讀性、可移植性和易理解等優(yōu)點，并通過Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過下載到FPGA 芯片后，可應用于實際的數字鐘顯示中...

  標簽： Verilog HDL 多功能 數字

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• This documentation is based on the following versions:- pre-release of the wimax model developed by免費下載

  資源簡介：This documentation is based on the following versions:- pre-release of the wimax model developed by NIST (file patch-wimax-prerelease-092206)- ns-2.29 此程序是NS2下用C、C++編寫的，主要對Wimax 802.16d和802.16e的MAC層協議的仿真，壓縮文件內...

  標簽： documentation pre-release developed following

  上傳時間： 2014-01-12

  上傳用戶：釣鰲牧馬

• 基于DSP Builder數字信號處理器的FPGA設計免費下載

  資源簡介：針對使用硬件描述語言進行設計存在的問題，提出一種基于FPGA并采用DSP Builder作為設計工具的數字信號處理器設計方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ設計流程，設計了一個12階FIR 低通數字濾波器，通過Quartus 時序仿真及嵌入式邏輯分析儀Sign...

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• 51單片機電子時鐘含proteus仿真和keil...免費下載

  資源簡介：說明：? 51單片機電子時鐘，含proteus仿真和keil工程源碼(51 single-chip electronic clock, including the proteus simulation and keil project source)

  標簽： 51單片機 電子時鐘 proteus

  上傳時間： 2022-05-27

  上傳用戶：

• 電子時鐘用c51單片機帶Proteus仿真以及...免費下載

  資源簡介：說明：? 電子時鐘，用c51單片機，帶Proteus仿真以及匯編的源碼。(electronic clock)

  標簽： 電子時鐘 c51 單片機 proteus

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• 學習用PSPICE設計模電實驗免費下載

  資源簡介：1.創(chuàng)建一個新項目：激活design Manager，在菜單File中選擇New Workspace，然后填入項目名稱expl。2.輸入網單文件：在Tools菜單中選擇TextEdit，輸入如下所示的網單文件。3.保存文件：將文件命名為expl.cir。4.對電路進行模擬：在Tools菜單中選擇PspiceA/D，再...

  標簽： pspice

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• A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation免費下載

  資源簡介：A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.

  標簽： simulation Verilog writing clock

  上傳時間： 2016-10-12

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• clock for any purpose of use by any design免費下載

  資源簡介：clock for any purpose of use by any design

  標簽： any purpose design clock

  上傳時間： 2014-01-06

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• A code writing by Verilog which can find medium value. With a C file to see the simulation results.免費下載

  資源簡介：A code writing by Verilog which can find medium value. With a C file to see the simulation results. A co-design example of C and Verilog.

  標簽： simulation Verilog writing results

  上傳時間： 2014-11-18

  上傳用戶：ljt101007

• This is an extension of sign example. You can design your own traffic sign by using Verilog. And the免費下載

  資源簡介：This is an extension of sign example. You can design your own traffic sign by using Verilog. And the result from Verilog can be seen by the attached C file.

  標簽： sign extension Verilog example

  上傳時間： 2016-10-12

  上傳用戶：haohaoxuexi

• software that use for writing the coding, also work with MPLAB for compiler. (ouput .hex file that c免費下載

  資源簡介：software that use for writing the coding, also work with MPLAB for compiler. (ouput .hex file that can be use for design circuit (Proteus))

  標簽： that for software compiler

  上傳時間： 2013-12-02

  上傳用戶：daguda

• DESCRIPTION: DDS design BY PLD DEVICES免費下載

  資源簡介：* DESCRIPTION: DDS design BY PLD DEVICES.\r\n *\r\n * AUTHOR: Sun Yu\r\n *\r\n * HISTORY: 12/06/2002 \r\n *

  標簽： DESCRIPTION DEVICES design DDS

  上傳時間： 2013-09-09

  上傳用戶：jokey075

• hex file to bin file convert tool免費下載

  資源簡介：hex file to bin file convert tool

  標簽： file convert tool hex

  上傳時間： 2014-01-20

  上傳用戶：moerwang

• 這是一個介紹design By Contract的PPT文件免費下載

  資源簡介：這是一個介紹design By Contract的PPT文件

  標簽： Contract design By

  上傳時間： 2014-01-12

  上傳用戶：zsjzc

• this is a trade sale system realized by java. It can run some easy functions and has a good design p免費下載

  資源簡介：this is a trade sale system realized by java. It can run some easy functions and has a good design pattern CVS. A good project to learn CVS.

  標簽： functions realized design system

  上傳時間： 2015-04-17

  上傳用戶：sz_hjbf

• by java , to read, write and modify excel file免費下載

  資源簡介：by java , to read, write and modify excel file

  標簽： modify excel write java

  上傳時間： 2014-09-09

  上傳用戶：woshiayin

• USB design By Example免費下載

  資源簡介：USB design By Example

  標簽： Example design USB By

  上傳時間： 2013-12-03

  上傳用戶：zgu489

• A Huffman implementation reference design in both VHDL and Verilog is provided by the Xilinx免費下載

  資源簡介：A Huffman implementation reference design in both VHDL and Verilog is provided by the Xilinx

  標簽： implementation reference provided Huffman

  上傳時間： 2015-07-07

  上傳用戶：cooran

• -- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can r免費下載

  資源簡介：-- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can redistribute it and/or -- modify it and/or implement it after contacting the author -- You can check the draft license at

  標簽： design combinational Shifter Barrel

  上傳時間： 2014-12-21

  上傳用戶：784533221

• 操作系統(tǒng)設計與實作第三版 Operating Systems design and Implementation, Third Edition By Andrew S. Tanenbaum 絕對經典的免費下載

  資源簡介：操作系統(tǒng)設計與實作第三版 Operating Systems design and Implementation, Third Edition By Andrew S. Tanenbaum 絕對經典的一本兼具實作操作系統(tǒng)與講述原理的書想要操作系統(tǒng)實作的功力大增就靠這本書

  標簽： S. Implementation Operating Tanenbaum

  上傳時間： 2013-12-12

  上傳用戶：498732662

• electronic design automation (EDA) company providing logic synthesis and analysis tools for FPGA and免費下載

  資源簡介：electronic design automation (EDA) company providing logic synthesis and analysis tools for FPGA and ASIC designers.

  標簽： electronic automation and providing

  上傳時間： 2014-01-10

  上傳用戶：四只眼

• A part public bus simulation system, mainly about map design, java file, groupwork, helpful to the b免費下載

  資源簡介：A part public bus simulation system, mainly about map design, java file, groupwork, helpful to the beginners

  標簽： simulation groupwork helpful mainly

  上傳時間： 2014-01-06

  上傳用戶：變形金剛