替代加密: A B C D E F G H I J K L M N O P Q R S T U V W 密文 Y Z D M R N H X J L I O Q U W A C B E G F K P 明文 X Y Z T S V I HAVE A DREAM！# 密文？？ 用ARM編程實(shí)現(xiàn)替代加密。
標(biāo)簽： 加密
上傳時(shí)間： 2016-07-17
上傳用戶：qq521
在C8051中用I/O口模擬SPI的C代碼.
上傳時(shí)間： 2013-12-17
上傳用戶：498732662
cmac 訓(xùn)練簡單線性函數(shù)程序,z = sin(x + y),為c++程序
上傳時(shí)間： 2013-12-27
上傳用戶：bakdesec
linux組播代碼 #! /bin/sh gcc -Wall mcastclient.c -o mcastclient gcc -Wall mcastserver.c -o mcastserver #./mcastserver 230.1.1.1 7838 #./mcastclient 230.1.1.1 7838 192.168.100.1 12345
標(biāo)簽： mcastclient Wall mcastserver mcastserve
上傳時(shí)間： 2013-12-20
上傳用戶：lepoke
Arduino 數(shù)位I/O的標(biāo)準(zhǔn)測試程式，利用讀取輸入的數(shù)位訊來控制輸出的數(shù)位訊號(hào)，文中有詳細(xì)的描述與介紹說明。
上傳時(shí)間： 2017-05-23
上傳用戶：6546544
Stanley B Lippman和J o s é e L a j o i e寫的c++ primer 中文版（第三版）。
標(biāo)簽： Stanley Lippman primer
上傳時(shí)間： 2017-06-12
上傳用戶：talenthn
CC = gcc clist: clist.c $(CC) `gtk-config --cflags` clist.c -o clist `gtk-config --libs` clean: rm -f *.o clist *.bak
標(biāo)簽： clist gtk-config cflags CC
上傳時(shí)間： 2017-06-12
上傳用戶：開懷常笑
c++ Ngô n ngữ C cho vi đ iề u khiể n Các tài liệ u tham khả o, ebook. Programming Microcontrollers in C (Ted Van Sickle) C Programming for Microcontrollers (Joe Pardue SmileyMicros.com ) Programming 16-Bit PIC Microcontrollers in C (Jucio di jasio ) C Programming for AVR Programming embedded system I,II (Michael J . Pont ) ( các tài liệ u này đ ã down load về )
上傳時(shí)間： 2017-07-29
上傳用戶：壞壞的華仔
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶：wxqman
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