XILINX FPGA ISE 下載教程，基于ISE 14.7軟件詳細(xì)講解基于ISE環(huán)境下載.bit文件和配置Flash文件的方法
標(biāo)簽： xilinx fpga ise CPLD
上傳時(shí)間： 2022-07-04
上傳用戶：
開(kāi)關(guān)電源基本原理與設(shè)計(jì)介紹，臺(tái)達(dá)的資料，很好的
標(biāo)簽： 開(kāi)關(guān) 電源基本
上傳時(shí)間： 2013-04-24
上傳用戶：cursor
開(kāi)關(guān)電源設(shè)計(jì)資料
標(biāo)簽： 開(kāi)關(guān)電源 設(shè)計(jì)實(shí)例 調(diào)試
上傳時(shí)間： 2013-11-08
上傳用戶：李哈哈哈
怎樣寫testbench-xilinx 在ISE 環(huán)境中， 當(dāng)前資源操作窗顯示了資源管理窗口中選中的資源文件能進(jìn)行的相關(guān)操作。在資源管理窗口選中了 testbench 文件后，在當(dāng)前資源操作窗顯示的 ModelSim Simulator 中顯示了4種能進(jìn)行的模擬操作，分別是：Simulator Behavioral Model（功能仿真）、Simulator Post-translate VHDL Model（翻譯后仿真）、Simulator Post-Map VHDL Model（映射后仿真）、Simulator Post-Place & Route VHDL Model（布局布線后仿真） 。如
標(biāo)簽： testbench-xilinx
上傳時(shí)間： 2013-11-14
上傳用戶：467368609
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
本教程主要是向 ISE 的初學(xué)者描述和演示, 在 XILINX 的 ISE 集成軟件環(huán)境中 如何用 VHDL 和原理圖的方式進(jìn)行設(shè)計(jì)輸入 如何用 ModelSim 仿真工具對(duì)設(shè)計(jì)進(jìn)行功能仿真和時(shí) 序仿真 如何實(shí)現(xiàn)設(shè)計(jì)
上傳時(shí)間： 2013-11-06
上傳用戶：qzhcao
電子發(fā)燒友網(wǎng)：針對(duì)目前電子發(fā)燒友網(wǎng)舉辦的“玩轉(zhuǎn)FPGA：iPad2，賽靈思開(kāi)發(fā)板等你拿”，小編在電話回訪過(guò)程中留意到有很多參賽選手對(duì)Xilinx 公司的FPGA及其設(shè)計(jì)流程不是很熟悉，所以特意在此整理了一些相關(guān)知識(shí)，希望對(duì)大家有所幫助。當(dāng)然也希望Xilinx FPGA愛(ài)好者能跟我們一起來(lái)探討學(xué)習(xí)！ 本文主要幫助大家熟悉利用ISE進(jìn)行Xilinx 公司FPGA 代碼開(kāi)發(fā)的基本流程。主要是幫助初學(xué)者了解和初步掌握 ISE 的使用，不需要 FPGA 的開(kāi)發(fā)基礎(chǔ)，所以對(duì)每個(gè)步驟并不進(jìn)行深入的討論。 圖 實(shí)例顯示成果圖
標(biāo)簽： Xilinx FPGA 設(shè)計(jì)實(shí)例
上傳時(shí)間： 2013-11-06
上傳用戶：時(shí)代將軍
特點(diǎn) 精確度0.1%滿刻度 ±1位數(shù) 可量測(cè) 交直流電流/交直流電壓/電位計(jì)/傳送器/Pt-100/荷重元/電阻 等信號(hào) 顯示范圍-1999-9999可任意規(guī)劃 具有異常值與異常次數(shù)記錄保留功能 異常信號(hào)過(guò)高或過(guò)低或范圍內(nèi)或范圍外檢測(cè)可任意設(shè)定 報(bào)警繼電器復(fù)歸方式可任意設(shè)定 尺寸小,穩(wěn)定性高 2.主要規(guī)格 精確度: 0.1% F.S. ±1 digit 0.2% F.S. ±1 digit(AC) 取樣時(shí)間: 16 cycles/sec. 顯示值范圍: -1999 - +9999 digit adjustable 啟動(dòng)延遲動(dòng)作時(shí)間: 0-99.9 second adjustable 繼電器延遲動(dòng)作時(shí)間: 0-99.9 second adjustable 繼電器復(fù)歸方式: Manual (N) / latch(L) can be modified 繼電器動(dòng)作方向: HI /LO/GO/HL can be modified 繼電器容量: AC 250V-5A, DC 30V-7A 過(guò)載顯示: "doFL" 溫度系數(shù): 50ppm/℃ (0-50℃) 顯示幕: Red high efficiency LEDs high 14.22mm(.56")(PV) Red high efficiency LEDs high 7.0mm(.276")(NO) 參數(shù)設(shè)定方式: Touch switches 記憶型式 : Non-volatile E2PROM memory 絕緣耐壓能力: 2KVac/1 min. (input/output/power) 1600Vdc(input/output 使用環(huán)境條件 : 0-50℃(20 to 90% RH non-condensed) 存放環(huán)境條件: 0-70℃(20 to 90% RH non-condensed) CE認(rèn)證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
上傳時(shí)間： 2013-11-02
上傳用戶：fandeshun
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶：wxqman
本教程主要是向 ISE 的初學(xué)者描述和演示, 在 XILINX 的 ISE 集成軟件環(huán)境中 如何用 VHDL 和原理圖的方式進(jìn)行設(shè)計(jì)輸入 如何用 ModelSim 仿真工具對(duì)設(shè)計(jì)進(jìn)行功能仿真和時(shí) 序仿真 如何實(shí)現(xiàn)設(shè)計(jì)
上傳時(shí)間： 2013-10-12
上傳用戶：gxrui1991
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