This book evolved over the past ten years from a set of lecture notes developed while teaching the undergraduate Algorithms course at Berkeley and U.C. San Diego. Our way of teaching this course evolved tremendously over these years in a number of directions, partly to address our students' background (undeveloped formal skills outside of programming), and partly to reect the maturing of the eld in general, as we have come to see it. The notes increasingly crystallized into a narrative, and we progressively structured the course to emphasize the ?story line? implicit in the progression of the material. As a result, the topics were carefully selected and clustered. No attempt was made to be encyclopedic, and this freed us to include topics traditionally de-emphasized or omitted from most Algorithms books.
標簽： Algorithms 算法
上傳時間： 2013-11-11
上傳用戶：JamesB
飛思卡爾智能車的舵機測試程序 #include <hidef.h> /* common defines and macros */#include <MC9S12XS128.h> /* derivative information */#pragma LINK_INFO DERIVATIVE "mc9s12xs128" void SetBusCLK_16M(void) { CLKSEL=0X00; PLLCTL_PLLON=1; //鎖相環電路允許位 SYNR=0x00 | 0x01; //SYNR=1 REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK==1)); CLKSEL_PLLSEL =1; } void PWM_01(void) { //舵機初始化 PWMCTL_CON01=1; //0和1聯合成16位PWM； PWMCAE_CAE1=0; //選擇輸出模式為左對齊輸出模式 PWMCNT01 = 0; //計數器清零； PWMPOL_PPOL1=1; //先輸出高電平，計數到DTY時，反轉電平 PWMPRCLK = 0X40; //clockA 不分頻,clockA=busclock=16MHz;CLK B 16分頻:1Mhz PWMSCLA = 0x08; //對clock SA 16分頻,pwm clock=clockA/16=1MHz; PWMCLK_PCLK1 = 1; //選擇clock SA做時鐘源 PWMPER01 = 20000; //周期20ms； 50Hz; PWMDTY01 = 1500; //高電平時間為1.5ms; PWME_PWME1 = 1;
上傳時間： 2013-11-04
上傳用戶：狗日的日子
目錄 C語言基礎知識 C 語言簡介 C 語言的特點… C 語言的發展和標準化…數據類型、運算、表達式和編譯預處理 數據類型… 基本類型與數據表示 整數類型和整數的表示… 實數類型和實數的表示… 字符類型和字符的表示… 運算符、表達式與計算… 算術運算符 算術表達式 表達式的求值… 變量——概念、定義和使用… 變量的定義0 變量的使用：取值與賦值 預處理 文件包含命令… 宏定義與宏替換…邏輯判斷與運算… 關系運算和邏輯運算 復雜條件的描述0 i f語句循環控制 whi le語句 for語句… 循環程序常用的若干機制 增量和減量運算符（++、--） 逗號運算符 控制結構和控制語句 do-while循環結構… 流程控制語句… goto語句… 開關語句…函數 概述… 函數定義和程序的函數分解… 函數定義… 函數調用…數組 數組的概念、定義和使用 數組變量定義… 數組的使用 數組的初始化…結構 結構（struct） 結構說明與變量定義 結構變量的初始化和使用 結構與函數 處理結構的函數0指針 指針的概念 指針操作… 指針作為函數的參數 與指針有關的一些問題… 指針與數組 指向數組元素的指針 基于指針運算的數組程序設計 數組參數與指針 字符指針與字符數組0
上傳時間： 2013-11-16
上傳用戶：asdkin
//------------------------------------------------------------------------------------//此程序為ADC轉換程序，可以選擇向ADC0BUSY寫1或用定時器0,1,2,3作為ADC的啟動信號。////------------------------------------------------------------------------------------//頭文件定義//------------------------------------------------------------------------------------//#include <c8051f330.h> #include <stdio.h> //-----------------------------------------------------------------------------// 定義16位特殊功能寄存器//----------------------------------------------------------------------------- sfr16 ADC0 = 0xbd; sfr16 TMR0RL = 0xca; sfr16 TMR1RL = 0xca; sfr16 TMR2RL =0xca; sfr16 TMR3RL =0xca; sfr16 TMR0 = 0xCC; sfr16 TMR1 = 0xCC; sfr16 TMR2 = 0xcc; sfr16 TMR3 = 0xcc; //-----------------------------------------------------------------------------// 全局變量定義//-----------------------------------------------------------------------------char i;int result; //-----------------------------------------------------------------------------//定義常量//-----------------------------------------------------------------------------#define SYSCLK 49000000 #define SAMPLE_RATE 50000 //------------------------------------------------------------------------------------// 定義函數//------------------------------------------------------------------------------------void SYSCLK_Init (void);void PORT_Init (void);void Timer0_Init (int counts);void Timer1_Init (int counts);void Timer2_Init (int counts);void Timer3_Init (int counts);void ADC0_Init(void);void ADC0_ISR (void);void ADC0_CNVS_ADC0h(void);//------------------------------------------------------------------------------------// 主程序//------------------------------------------------------------------------------------ void main (void) { int ADCRESULT[50] ; int k; PCA0MD &= ~0x40; // 禁止看門狗 SYSCLK_Init (); PORT_Init (); Timer0_Init (SYSCLK/SAMPLE_RATE); //Timer1_Init (SYSCLK/SAMPLE_RATE); //選擇相應的啟動方式 //Timer2_Init (SYSCLK/SAMPLE_RATE); //Timer3_Init (SYSCLK/SAMPLE_RATE); ADC0_Init(); EA=1; while(1) { //ADC0_CNVS_ADC0h(); k=ADC0; ADCRESULT[i]=result; //此處設斷點，觀察ADCRESULT的結果 } }
上傳時間： 2013-10-13
上傳用戶：SimonQQ
溫濕度傳感器 sht11 仿真程序 sbit out =P3^0; //加熱口 //sbit input =P1^1;//檢測口 //sbit speek =P2^0;//報警 sbit clo =P3^7;//時鐘 sbit ST =P3^5;//開始 sbit EOC =P3^6;//成功信號 sbit gwei =P3^4;//個位 sbit swei =P3^3;//十位 sbit bwei =P3^2;//百位 sbit qwei =P3^1;//千位 sbit speak =P0^0;//報警音 sbit bjled =P0^1;//報警燈 sbit zcled =P0^2;//正常LED int count; uchar xianzhi;//取轉換結果 uchar seth;//高時間 uchar setl;//低時間 uchar seth_mi;//高時間 uchar setl_mi;//低時間 bit hlbz;//高低標志 bit clbz; bit spbz; ///定時中斷程序/// void t0 (void) interrupt 1 using 0 { TH0=(65536-200)/256;//5ms*200=1000ms=1s TL0=(65536-200)%256; clo=!clo;//產生時鐘 if(count>5000) { if(hlbz) { if(seth_mi==0){seth_mi=seth;hlbz=0;out=0;} else seth_mi--; } if(!hlbz) { if(setl_mi==0){setl_mi=setl;hlbz=1;out=1;} else setl_mi--; } count=0; } else count++; } ///////////// ///////延時/////// delay(int i) { while(--i); } ///////顯示處理/////// xianshi() { int abcd=0; int i; for (i=0;i<5;i++) { abcd=xianzhi; gwei=1; swei=1; bwei=1; qwei=1; P1=dispcode[abcd/1000]; qwei=0; delay(70); qwei=1; abcd=abcd%1000; P1=dispcode[abcd/100]; bwei=0; delay(70); bwei=1; abcd=abcd%100; P1=dispcode[abcd/10]; swei=0; delay(70); swei=1; abcd=abcd%10; P1=dispcode[abcd]; gwei=0; delay(70); gwei=1; } } doing() { if(xianzhi>100) {bjled=0;speak=1;zcled=1;} else {bjled=1;speak=0;zcled=0;} } void main(void) { seth=60;//h60秒 setl=90;//l90秒 seth_mi=60;//h60秒 setl_mi=90;//l90秒 TMOD=0X01;//定時0 16位工作模式 TH0=(65536-200)/256; TL0=(65536-200)%256; TR0=1; //開始計時 ET0=1; //開定時0中斷 EA=1; //開全中斷 while(1) { ST=0; _nop_(); ST=1; _nop_(); ST=0; // EOC=0; xianshi(); while(!EOC) { xianshi(); } xianzhi=P2; xianshi(); doing(); } }
上傳時間： 2013-11-07
上傳用戶：我們的船長
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
The standard that governs the design of avioniccomponents and systems, DO-254, is one of the mostpoorly understood but widely applicable standardsin the avionic industry. While information on thegeneral aspects of the standard is easy to obtain, thedetails of exactly how to implement the standard aresketchy. And once an entity develops a process thatachieves compliance, the details of how compliancewas achieved become part of the intellectualproperty of that entity. This white paper focuses onthe details of developing a DO-254 compliantprocess for the design of FPGAs.
上傳時間： 2013-11-03
上傳用戶：ysystc670
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時間： 2014-11-26
上傳用戶：erkuizhang
We would like to welcome you as a user of the Allegro CX, a rugged, handheld fi eld PC for data collection. Developed with the input of data collection professionals worldwide, the Allegro CX is adaptable and versatile for use in a wide variety of data collection environments. The Allegro CX continues to utilize our ergonomic, lightweight design that is standard in our line of Allegro Field PCs. This design makes your Allegro easy to use for extended periods while moving to and from data collection sites in the fi eld.
上傳時間： 2015-01-02
上傳用戶：zhangyi99104144
波長信號的解調是實現光纖光柵傳感網絡的關鍵，基于現有的光纖光柵傳感器解調方法，提出一種基于FPGA的雙匹配光纖光柵解調方法，此系統是一種高速率、高精度、低成本的解調系統，并且通過引入雙匹配光柵有效地克服了雙值問題同時擴大了檢測范圍。分析了光纖光柵的測溫原理并給出了該方案軟硬件設計，綜合考慮系統的解調精度和FPGA的處理速度給出了基于拉格朗日的曲線擬合算法。 Abstract: Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This paper analyzes the principle of fiber Bragg grating temperature and gives the software and hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this paper gives the curve fitting algorithm based on Lagrange.
上傳時間： 2013-10-10
上傳用戶：zxc23456789
