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  • This code was developed by my techer. :D

    This code was developed by my techer. :D

    標簽: developed techer This code

    上傳時間: 2013-12-29

    上傳用戶:lnnn30

  • This file was based on: drivers/ata/pata_ixp4xx_cf.c

    This file was based on: drivers/ata/pata_ixp4xx_cf.c

    標簽: pata_ixp drivers based xx_cf

    上傳時間: 2013-12-10

    上傳用戶:lepoke

  • This are the code of some of the projects that I was able to make

    This are the code of some of the projects that I was able to make

    標簽: the projects This able

    上傳時間: 2014-01-15

    上傳用戶:haohaoxuexi

  • AAC編解碼源碼

    ·詳細說明:AAC編解碼源碼,Advanced Audio (AAC) Decoder including SBR decoding,(mp3已經過時了,這是包含SBR的最新AAC編解碼算法)-AAC encode/decode source . Advanced Audio (AAC) Decoder including SBR decoding. Mp3 was out. This packag

    標簽: AAC 編解碼 源碼

    上傳時間: 2013-08-01

    上傳用戶:litianchu

  • This brief introduce a kind of the framework construction to materialize the system. And an example

    This brief introduce a kind of the framework construction to materialize the system. And an example was given with the discussion on the performence.

    標簽: construction materialize introduce framework

    上傳時間: 2013-08-17

    上傳用戶:ysystc699

  • US Navy VHDL Modelling Guide

      This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.

    標簽: Modelling Guide Navy VHDL

    上傳時間: 2014-12-23

    上傳用戶:xinhaoshan2016

  • 信號鏈和PLC是如何影響我們的生活

    Abstract: It is incredible how many programmable logic controls (PLCs) around us make our modern life possible and pleasant.Machines in our homes heat and cool our air and water, as well as preserve and cook our food. This tutorial explains the importanceof PLCs, and describes how to choose component parts using the parametric tools on the Maxim's website.A similar version of this article was published February 29, 2012 in John Day's Automotive Electronic News.

    標簽: PLC 信號鏈

    上傳時間: 2013-11-10

    上傳用戶:liaocs77

  • 簡單的多輸出范圍16位DAC設計

      Precision 16-bit analog outputs with softwareconfigurableoutput ranges are often needed in industrialprocess control equipment, analytical and scientificinstruments and automatic test equipment. In the past,designing a universal output module was a daunting taskand the cost and PCB real estate associated with thisfunction were problematic, if not prohibitive.

    標簽: DAC 輸出范圍

    上傳時間: 2014-12-23

    上傳用戶:如果你也聽說

  • LTC1099基于PC的數據采集板實現

    A complete design for a data acquisition card for the IBM PC is detailed in this application note. Additionally, C language code is provided to allow sampling of data at speed of more than 20kHz. The speed limitation is strictly based on the execution speed of the "C" data acquisition loop. A "Turbo" XT can acquire data at speeds greater than 20kHz. Machines with 80286 and 80386 processors can go faster than 20kHz. The computer that was used as a test bed in this application was an XT running at 4.77MHz and therefore all system timing and acquisition time measurements are based on a 4.77MHz clock speed.

    標簽: 1099 LTC 數據 采集板

    上傳時間: 2013-10-29

    上傳用戶:BOBOniu

  • 光電轉換電路設計

    OPTOELECTRONICS CIRCUIT COLLECTION AVALANCHE PHOTODIODE BIAS SUPPLY 1Provides an output voltage of 0V to +80V for reverse biasingan avalanche photodiode to control its gain. This circuit canalso be reconfigured to supply a 0V to –80V output.LINEAR TEC DRIVER–1This is a bridge-tied load (BTL) linear amplifier for drivinga thermoelectric cooler (TEC). It operates on a single +5Vsupply and can drive ±2A into a common TEC.LINEAR TEC DRIVER–2This is very similar to DRIVER–1 but its power output stagewas modified to operate from a single +3.3V supply in orderto increase its efficiency. Driving this amplifier from astandard +2.5V referenced signal causes the output transistorsto have unequal power dissipation.LINEAR TEC DRIVER–3This BTL TEC driver power output stage achieves very highefficiency by swinging very close to its supply rails, ±2.5V.This driver can also drive ±2A into a common TEC. Operationis shown with the power output stage operating on±1.5V supplies. Under these conditions, this linear amplifiercan achieve very high efficiency. Application ReportThe following collection of analog circuits may be useful in electro-optics applications such as optical networkingsystems. This page summarizes their salient characteristics.

    標簽: 光電轉換 電路設計

    上傳時間: 2013-10-27

    上傳用戶:落花無痕

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