數(shù)字邊沿鑒相器 verilog源程序
標(biāo)簽: verilog 數(shù)字 鑒相器 源程序
上傳時間: 2014-12-07
上傳用戶:爺?shù)臍赓|(zhì)
Verilog and VHDL狀態(tài)機設(shè)計,英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.
標(biāo)簽: Verilog VHDL and 狀態(tài)
上傳時間: 2013-12-19
上傳用戶:change0329
Verilog 程序例子 王金明:《Verilog HDL程序設(shè)計教程》程序例子,帶說明。
上傳時間: 2014-01-08
上傳用戶:star_in_rain
用verilog設(shè)計密勒解碼器 一、題目: 設(shè)計一個密勒解碼器電路 二、輸入信號: 1. DIN:輸入數(shù)據(jù) 2. CLK:頻率為2MHz的方波,占空比為50% 3. RESET:復(fù)位信號,低有效 三、輸入信號說明: 輸入數(shù)據(jù)為串行改進(jìn)密勒碼,每個碼元持續(xù)時間為8μs,即16個CLK時鐘;數(shù)據(jù)流是由A、B、C三種信號組成; A:前8個時鐘保持“1”,接著5個時鐘變?yōu)椤?”,最后3個時鐘為“1”。 B:在整個碼元持續(xù)時間內(nèi)都沒有出現(xiàn)“0”,即連續(xù)16個時鐘保持“1”。 C:前5個時鐘保持“0”,后面11個時鐘保持“1”。 改進(jìn)密勒碼編碼規(guī)則如下: 如果碼元為邏輯“1”,用A信號表示。 如果碼元為邏輯“0”,用B信號表示,但以下兩種特例除外:如果出現(xiàn)兩個以上連“0”,則從第二個“0”起用C信號表示;如果在“通信起始位”之后第一位就是“0”,則用C信號表示,以下類推; “通信起始位”,用C信號表示; “通信結(jié)束位”,用“0”及緊隨其后的B信號表示。 “無數(shù)據(jù)”,用連續(xù)的B信號表示。
標(biāo)簽: verilog 2MHz DIN CLK
上傳時間: 2013-12-02
上傳用戶:wang0123456789
In this paper, we describe the development of a mobile butterfly-watching learning (BWL) system to realize outdoor independent learning for mobile learners. The mobile butterfly-watching learning system was designed in a wireless mobile ad-hoc learning environment. This is first result to provide a cognitive tool with supporting the independent learning by applying PDA with wireless communication technology to extend learning outside of the classroom. Independent learning consists of self-selection, self-determination, self-modification, and self-checking.
標(biāo)簽: butterfly-watching development describe learning
上傳時間: 2014-11-26
上傳用戶:waizhang
Our approach to understanding mobile learning begins by describing a dialectical approach to the development and presentation of a task model using the sociocognitive engineering design method. This analysis synthesises relevant theoretical approaches. We then examine two field studies which feed into the development of the task model.
標(biāo)簽: approach understanding dialectical describing
上傳時間: 2014-11-28
上傳用戶:comua
Verilog教程中文版
上傳時間: 2014-01-22
上傳用戶:lx9076
aes算法的verilog hdl實現(xiàn),供給大家作為參考 。
上傳時間: 2013-12-18
上傳用戶:gundan
verilog HDL picoblaze07.3.20
標(biāo)簽: picoblaze verilog HDL 07
上傳時間: 2015-09-26
上傳用戶:zyt
這個verilog代碼是一個輸入輸出經(jīng)典的例子。大家一起參考。
上傳時間: 2015-09-27
上傳用戶:爺?shù)臍赓|(zhì)
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