This project is created using the Keil ARM CA Compiler. The Logic Analyzer built into the simulator may be used to monitor and display any variable or peripheral I/O register. It is already configured to show the PWM output signal on PORT3.0 and PORT3.1 This ARM Example may be debugged using only the uVision Simulator and your PC--no additional hardware or evaluation boards are required. The Simulator provides cycle-accurate simulation of all on-chip peripherals of the ADuC7000 device series. You may create various input signals like digital pulses, sine waves, sawtooth waves, and square waves using signal functions which you write in C. Signal functions run in the background in the simulator within timing constraints you configure. In this example, several signal functions are defined in the included Startup_SIM.INI file.
標簽： the Analyzer Compiler project
上傳時間： 2013-12-19
上傳用戶：Yukiseop
ZigBee™ 是專為低速率傳感器和控制網絡設計的無線網絡協議。有許多應用可從ZigBee 協議受益，其中可能的一些應用有：建筑自動化網絡、住宅安防系統、工業控制網絡、遠程抄表以及PC 外設。此程序包提供的是Zigbee協義棧函數庫源代碼，它實現了一個與物理層 無關的應用程序接口。 因此，無需做重大修改就可以輕松地在射頻（Radio Frequency，RF）收發器之間移植應用程序。
上傳時間： 2014-01-16
上傳用戶：Pzj
Random Number Generators（隨機數生成）包括gaussian random number generator、uniform random number generator、low-frequency hold generator、1/f noise generator等5種隨機信號生成的c源代碼
標簽： generator random number Generators
上傳時間： 2014-12-07
上傳用戶：edisonfather
頻率調制，It is a diffrent matlab code for frequency modulation.
上傳時間： 2015-05-30
上傳用戶：wanqunsheng
These instructions assume that the 1.4 versions of the java and appletviewer commands are in your path. If they aren t, then you should either specify the complete path to the commands or update your PATH environment variable as described in the installation instructions for the Java 2 SDK.
標簽： instructions appletviewer the commands
上傳時間： 2015-06-01
上傳用戶：3到15
Routine mampres: To obtain amplitude response from h(exp(jw)). input parameters: h :n dimensioned complex array. the frequency response is stored in h(0) to h(n-1). n :the dimension of h and amp. fs :sampling frequency (Hz). iamp:If iamp=0: The Amplitude Res. amp(k)=abs(h(k)) If iamp=1: The Amplitude Res. amp(k)=20.*alog10(abs(h(k))). output parameters: amp :n dimensioned real array. the amplitude-frequency response is stored in amp(0) to amp(n-1). Note: this program will generate a data file "filename.dat" . in chapter 2
標簽： dimensione parameters amplitude response
上傳時間： 2013-12-19
上傳用戶：xfbs821
Rotating shafts experience a an elliptical motion called whirl. It is important to decompose this motion into a forward and backward whil orbits. The current function makes use of two sensors to generate a bi-directional spectrogram. The method can be extended to any time-frequency distribution ％ ％ compute the forward/backward Campbell/specgtrogram ％ ％ INPUT: ％ y (n x 2) each column is measured from a different sensor ％ /////// ％ __ ％ |s1| y(:,1) ％ |__| ％ __ ％ / \ ________|/ ％ | | | s2 |/ y(:,2) ％ \____/ --------|/ ％ ％ Fs Sampling frequnecy ％ ％ OUTPUT: ％ B spectrogram/Campbel diagram ％ x x-axis coordinate vector (time or Speed) ％ y y-axis coordinate vector (frequency [Hz])
標簽： experience elliptical decompose important
上傳時間： 2015-06-23
上傳用戶：372825274
his project was built and tested with WinAVR-20060125. Make sure the MCU target define in the Makefiles corresponds to the AVR you are using!! To build the code, just install WinAVR and run "make" from the console in echomaster and echoslave subdirs. "make program" will program the device if you have a AVRISP attached. Remember to set the AVR device to at least 8MHz. The AVR may use the programmable clock from MC1319x, just remember to check if the MC1319x and SPI communication is working FIRST! Otherwise you wont get any clock signal to the AVR and then you can t program it or reset the fuses! The MC1319x has default clock output of 32kHz so you will have to set your programmer to a very low frequency (<=32kHz/4) to be able to program it while it is running on that!
標簽： the 20060125 project WinAVR
上傳時間： 2014-10-10
上傳用戶：yan2267246
關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
describes the most common terms used in radarsystems, such as range, range resolution, Doppler frequency, and coherency. The second part of this chapter develops the radar range equation in many of its forms. This presentation includes the low PRF, high PRF,search, bistatic radar, and radar equation with jamming.
標簽： range radarsystems resolution describes
上傳時間： 2015-08-05
上傳用戶：宋桃子
