該系統(tǒng)由單片機(jī)89S52控制模塊，程控寬帶放大模塊，整形模塊，F(xiàn)PGA內(nèi)頻率、相位差測(cè)量模塊等構(gòu)成，采用等精度測(cè)頻法測(cè)出頻率和周期，可測(cè)量有效值為0.01～5V，頻率范圍1Hz～20MHz信號(hào)的頻率、周期信號(hào)，精度高達(dá)10-6。采用計(jì)數(shù)法測(cè)量相位差，該系統(tǒng)可測(cè)量有效值0.5～5V，頻率10Hz～100kHz信號(hào)的相位差，精度為1°。系統(tǒng)功能由按鍵控制，測(cè)量結(jié)果實(shí)時(shí)顯示，人機(jī)界面友好。 Abstract: The system consists of the following functional blocks:89S52microcontroller controlling module,programmable amplifier module,comparator module,frequency and phase difference testing module in the FPGA.The system use the equal accuracy frequency-examining technique it measures frequency and circle of signal which its ranges is from1Hz to20MHz and the amplitude of which its range is from0.01Vrms to5Vrms,precision is up to10-6.Using of count method,the system detects the phase difference of signal,the amplitude of whic its range is from0.5Vrms to5Vrms and the frequency of which its ranges is from10Hz to100kHz,precision is up to1°,The system functions is controlled by certain keys,measurement results are displayed in real-time and it is friendly interface.
標(biāo)簽： 89S52 單片機(jī) 多功能 計(jì)數(shù)器
上傳時(shí)間： 2013-11-04
上傳用戶：CHINA526
基于幅移鍵控技術(shù)ASK（Amplitude-Shift Keying），以C8051F340單片機(jī)作為監(jiān)測(cè)終端控制器，C8051F330D單片機(jī)作為探測(cè)節(jié)點(diǎn)控制器，采用半雙工的通信方式，通過監(jiān)控終端和探測(cè)節(jié)點(diǎn)的無線收發(fā)電路，實(shí)現(xiàn)數(shù)據(jù)的雙向無線傳輸。收發(fā)電路采用直徑為0.8 mm的漆包線自行繞制成圓形空心線圈天線，天線直徑為（3.4±0.3）cm。試驗(yàn)表明，探測(cè)節(jié)點(diǎn)與監(jiān)測(cè)終端的通信距離為24 cm，通過橋接方式，節(jié)點(diǎn)收發(fā)功率為102 mW時(shí)，節(jié)點(diǎn)間的通信距離可達(dá)20 cm。與傳統(tǒng)無線收發(fā)模塊相比，該無線收發(fā)電路在受體積、功耗、成本限制的場(chǎng)合有廣闊的應(yīng)用前景。 Abstract: Based on ASK technology and with the C8051F340 and C8051F330D MCU as the controller， using half-duplex communication mode， this paper achieves bi-directional data transfer. Transceiver circuit constituted by enameled wire which diameter is 0.8mm and wound into a diameter （3.4±0.3） cm circular hollow coil antenna. Tests show that the communication distance between detection and monitoring of the terminal is 24cm，the distance is up to 20cm between two nodes when using the manner of bridging and the node transceiver power is 102mW. Compared with the conventional wireless transceiver modules， the circuit has wide application prospect in small size， low cost and low power consumption and other characteristics.
標(biāo)簽： C8051F 單片機(jī) 無線收發(fā) 電路設(shè)計(jì)
上傳時(shí)間： 2013-10-19
上傳用戶：xz85592677
The PCF8578 is a low power CMOS1 LCD row and column driver, designed to drive dotmatrix graphic displays at multiplex rates of 1:8, 1:16, 1:24 or 1:32. The device has40 outputs, of which 24 are programmable and configurable for the following ratios ofrows/columns: 32¤8, 24¤16, 16¤24 or 8¤32. The PCF8578 can function as a stand-alone LCDcontroller and driver for use in small systems. For larger systems it can be used inconjunction with up to 32 PCF8579s for which it has been optimized. Together these twodevices form a general purpose LCD dot matrix driver chip set, capable of driving displaysof up to 40960 dots. The PCF8578 is compatible with most microcontrollers andcommunicates via a two-line bidirectional bus (I2C-bus). Communication overhead isminimized by a display RAM with auto-incremented addressing and display bankswitching.
標(biāo)簽： 8578 PCF LCD 圖形點(diǎn)陣
上傳時(shí)間： 2013-10-23
上傳用戶：頂?shù)弥?/p>
1 FEATURES· Single chip LCD controller/driver· 1 or 2-line display of up to 24 characters per line, or2 or 4 lines of up to 12 characters per line· 5 ′ 7 character format plus cursor; 5 ′ 8 for kana(Japanese syllabary) and user defined symbols· On-chip:– generation of LCD supply voltage (external supplyalso possible)– generation of intermediate LCD bias voltages– oscillator requires no external components (externalclock also possible)· Display data RAM: 80 characters· Character generator ROM: 240 characters· Character generator RAM: 16 characters· 4 or 8-bit parallel bus or 2-wire I2C-bus interface· CMOS/TTL compatible· 32 row, 60 column outputs· MUX rates 1 : 32 and 1 : 16· Uses common 11 code instruction set· Logic supply voltage range, VDD - VSS: 2.5 to 6 V· Display supply voltage range, VDD - VLCD: 3.5 to 9 V· Low power consumption· I2C-bus address: 011101 SA0.
標(biāo)簽： 2116 PCF LCD 驅(qū)動(dòng)器芯片
上傳時(shí)間： 2013-11-08
上傳用戶：laozhanshi111
The CAT93C46 is a 1 kb Serial EEPROM memory device which isconfigured as either 64 registers of 16 bits (ORG pin at VCC) or 128registers of 8 bits (ORG pin at GND). Each register can be written (orread) serially by using the DI (or DO) pin. The CAT93C46 features aself−timed internal write with auto−clear. On−chip Power−On Resetcircuit protects the internal logic against powering up in the wrongstate.
上傳時(shí)間： 2013-11-20
上傳用戶：ynzfm
The MSP-FET430PIF is a Parallel Port interface (does not include target board) that is used to program and debug MSP430 FET tools and test boards through the JTAG interface. This interface is included in our FET tools, but sold without the development board. This interface uses a Parallel PC Port to communicate to the Debugger Software (IAR Kickstart software included) running on the PC. The interface uses the standard 14 pin header to communicate to the MSP430 device using the standard JTAG protocol. The flash memory can be erased and programmed in seconds with only a few keystrokes, and since the MSP430 flash is extremely low power, no external power supply is required. The tool has an integrated software environment and connects directly to the PC which greatly simplifies the set-up and use of the tool. The flash development tool supports development with all MSP430 flash parts. Features MSP430 debugging interface to connect a MSP430-Flash-device to a Parallel port on a PC Supports JTAG debug protocol (NO support for Spy-Bi-Wire (2-wire JTAG) debug protocol, Spy-Bi-Wire (2-wire JTAG) is supported by MSP-FET430UIF) Parallel Port cable and a 14-conductor target cable Full documentation on CD ROM Integrated IAR Kickstart user interface which includes: Assembler Linker Limulator Source-level debugger Limited C-compiler Technical specifications: Backwardly compatable with existing FET tool boards.
上傳時(shí)間： 2013-10-26
上傳用戶：fengweihao158@163.com
PICKIT™ 2 PROGRAMMER-TO-GO USER GUIDE The PICkit 2 Programmer-To-Go functionality allows a PIC MCU memory image to be downloaded into the PICkit 2 unit for later programming into a specific PIC MCU. No software or PC is required to program devices once the PICkit 2 unit is set up for Programming-To-Go. A USB power source for the PICkit 2 is all that is needed.
標(biāo)簽： PROGRAMMER-TO PICKIT 8482
上傳時(shí)間： 2013-10-29
上傳用戶：ca05991270
根據(jù)看門狗電路的原理，設(shè)計(jì)出簡(jiǎn)單適用、性能可靠的1TrL型看門狗電路以及價(jià)格低廉、性能可靠的微功耗CMOS型看門狗電路，同時(shí)還介紹了常用的uP監(jiān)視器O型看門狗電路。關(guān)鍵詞：看門狗電路；1TrL型；CMOS型Abstract：In accordance with the principle of WDT (Watch Dog Timer 1circuit，design a，IT．L type WTD circuit，it is a dimple an d applicable an d reliable on performanceo Design a CMOS type WTD circuit，it is low prices and mini-power consumption。Also the article describes a common uP type WTD circuit。Key word：WDT circuit；TFL type；CMOS typ e
上傳時(shí)間： 2013-11-05
上傳用戶：685
The LPC1700 Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with Scatter-Gather DMA off-loads many operations from the CPU.
標(biāo)簽： 1700 MIIM LPC 以太網(wǎng)
上傳時(shí)間： 2013-11-09
上傳用戶：geshaowei
Virtex-5, Spartan-DSP FPGAs Application Note This application note demonstrates how efficient implementations of Digital Up Converters(DUC) and Digital Down Converters (DDC) can be done by leveraging the Xilinx DSP IPportfolio for increased productivity and reduced time to development. Step-by-step instruction is given on how to perform system-level trade off analysis and develop the most efficient FPGA implementation, thus allowing engineers a flexible, low-cost and low-power alternative to ASSP technologies.
標(biāo)簽： Spartan-DSP Virtex FPGAs Ap
上傳時(shí)間： 2013-10-23
上傳用戶：raron1989
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