一個(gè)在FPGA芯片上實(shí)現(xiàn)UART功能的vhdl源代碼，提供了UART的集成
上傳時(shí)間： 2015-07-05
上傳用戶：杜瑩12345
Synchronous Resets? Asynchronous Resets?I am so confused!How will I ever know which to use? 復(fù)位信號的論文
標(biāo)簽： Resets Asynchronous Synchronous confused
上傳時(shí)間： 2015-07-05
上傳用戶：二驅(qū)蚊器
《Core Java2 Volume I-5e》 源碼
標(biāo)簽： Volume Java2 Core 源碼
上傳時(shí)間： 2015-07-06
上傳用戶：tb_6877751
基于FPGA的串行通信UART控制器，采用VHDL語言編寫，包含多個(gè)子模塊。 在ISE或FPGA的其它開發(fā)環(huán)境下新建一個(gè)工程，然后將文檔中的各個(gè)模塊程序添加進(jìn)去，即可運(yùn)行仿真。源程序已經(jīng)過本人的仿真驗(yàn)證。
上傳時(shí)間： 2013-12-08
上傳用戶：zhouchang199
This application note describes a method for developing block-oriented I/O device drivers for applications that use the DSP/BIOS real-time kernel and includes examples that run with Code Composer Studio v2.1 on the Texas Instruments TMS320C5402 and TMS320C6711 DSP Starter Kits (DSKs). The device driver model presented here has now been superceded with an updated version that supports not only block oriented devices, but also devices such as UARTs, PCI and USB buses and Multimedia cards. Documentation on the updated driver model as well as example drivers and source code can be found in the Device Driver Developer s Kit product now available for download from the TI Developer s Village.
標(biāo)簽： block-oriented application developing describes
上傳時(shí)間： 2015-07-07
上傳用戶：kelimu
This a set of notes I put together for my Computer Architecture class in 1990. Students had a project in which they had to model a microprocessor architecture of their choice. They used these notes to learn VHDL. The notes cover the VHDL-87 version of the language. Not all of the language is covered (about 95％). You may use this booklet for your own personal learning purposes. You may not use it for profit (eg, selling copies of it, using it in a course for which people pay, etc). If you want to make use of it beyond these conditions, contact me and we can come to some arrangement.
標(biāo)簽： Architecture Computer Students together
上傳時(shí)間： 2014-01-15
上傳用戶：wxhwjf
modelsim_se_tutorThis is a set of notes I put together for my Computer Architecture class in 1990. Students had a project in which they had to model a microprocessor architecture of their choice. They used these notes to learn VHDL. The notes cover the VHDL-87 version of the language. Not all of the language is covered (about 95％).
標(biāo)簽： modelsim_se_tutorThis Architecture Computer together
上傳時(shí)間： 2015-07-07
上傳用戶：xfbs821
This is a set of notes I put together for my Computer Architecture class in 1990. Students had a project in which they had to model a microprocessor architecture of their choice. They used these notes to learn VHDL. The notes cover the VHDL-87 version of the language. Not all of the language is covered (about 95％).
標(biāo)簽： Architecture Computer Students together
上傳時(shí)間： 2013-12-26
上傳用戶：kelimu
本書第一部分講述的是傳統(tǒng)的網(wǎng)絡(luò)接口N e t B I O S、重定向器以及通過重定向器進(jìn)行的各類 網(wǎng)絡(luò)通信。盡管本書大部分內(nèi)容均圍繞Wi n s o c k編程這一主題展開，但是， A P I比起Wi n s o c k 來，仍然具有某些獨(dú)到之處
標(biāo)簽： 分 定向 網(wǎng)絡(luò)接口 編程
上傳時(shí)間： 2015-07-08
上傳用戶：戀天使569
提供了一種簡單的單向“進(jìn)程間通信”（interprocess communication, I P C）機(jī)制。這個(gè)機(jī)制的名字非常古怪，叫作“郵槽”（M a i l s l o t）。用最簡單的話來說，通過 郵槽，客戶機(jī)進(jìn)程可將消息傳送或廣播給一個(gè)或多個(gè)服務(wù)器進(jìn)程。
標(biāo)簽： communication interprocess 機(jī)制 進(jìn)程間通信
上傳時(shí)間： 2014-01-26
上傳用戶：二驅(qū)蚊器
蟲蟲下載站版權(quán)所有 京ICP備2021023401號-1
<rt id="00w8c"></rt>
<rt id="00w8c"></rt>