The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second level cache, and maintain coherence at the L1 cache with a write-invalidate policy. The L2 cache is two-way set associative, with a block size of 8 words, and a total capacity of 512 words.
標(biāo)簽：
implementation
instruction
multiple
purpose
上傳時(shí)間：
2017-04-18
上傳用戶：731140412
