This example describes how to use the ADC and DMA to transfer continuously converted data from ADC to a data buffer. The ADC is configured to converts continuously ADC channel14. Each time an end of conversion occurs the DMA transfers, in circular mode, the converted data from ADC1 DR register to the ADC_ConvertedValue variable. The ADC1 clock is set to 14 MHz.
標(biāo)簽： continuously ADC describes converted
上傳時(shí)間： 2014-01-03
上傳用戶：徐孺
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.
標(biāo)簽： bus bidirectional primarily designed
上傳時(shí)間： 2013-12-11
上傳用戶：jeffery
It is not the intention of this application note to illustrate usage of the part in either of operational modes. The application note does not cover details on setting up for data transfers. After having reviewed this application note, the reader is expected to understand the data flow for and IN and OUT
標(biāo)簽： application illustrate intention the
上傳時(shí)間： 2013-12-09
上傳用戶：qoovoop
USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
標(biāo)簽： speed USBHostSlave and Supports
上傳時(shí)間： 2014-01-17
上傳用戶：sxdtlqqjl
The book describes the USB interfase and how to develop drivers, communications, power distribution, data transfers, packet definition and recovery and a software overview.
標(biāo)簽： communications distribution describes interfase
上傳時(shí)間： 2014-01-13
上傳用戶：tfyt
Mobile radio communications are evolving from pure telephony systems to multimedia platforms offering a variety of services ranging from simple file transfers and audio and video streaming, to interactive applications and positioning tasks. Naturally, these services have different constraints concerning data rate, delay, and reliability (quality-of-service (QoS)). Hence, future mobile radio systems have to provide a large flexibility and scal- ability to match these heterogeneous requirements.
標(biāo)簽： Communications Wireless Channels MIMO over
上傳時(shí)間： 2020-06-01
上傳用戶：shancjb
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