C++ Standard Library provides a set of common classes and interfaces that greatly extend the core C++ language. The library, however, is not self-explanatory. To make full use of its components-and to benefit from their power-you need a resource that does far more than list the classes and their functions. The C++ Standard Library not only provides comprehensive documentation of each library component, it also offers clearly written explanations of complex concepts, describes the practical programming details needed for effective use, and gives example after example of working code.
標(biāo)簽： interfaces Standard provides Library
上傳時間： 2014-03-01
上傳用戶：lizhizheng88
This software designs the student result management system m ay replace the tedious low effect the manual management, has realized the result management, the information management and the curriculum manages three big cores functions.
標(biāo)簽： the management software designs
上傳時間： 2013-12-15
上傳用戶：kr770906
This software designs the document management system may replace the tedious low effect the manual management, has used the c language programming, realized the document input to loan, the information management and the data compilation three big cores function
標(biāo)簽： the management software document
上傳時間： 2013-12-20
上傳用戶：yt1993410
c語言程序，將阿拉伯?dāng)?shù)字翻譯成英文。如輸入：792677321 輸出：seven hundred ninety-two million six hundred seventy-seven thousand three hundred twenty-one
上傳時間： 2014-01-03
上傳用戶：yyyyyyyyyy
This lab exercise will introduce you to the AccelWare IP generators. AccelWare is a library of over fifty IP generators, available in the form of three toolkits that produce synthesizable MATLAB for common MATLAB built in and toolbox functions. Each generator offers macro and micro-architecture selections that allow full customization of the generated model to the target application requirements.
標(biāo)簽： AccelWare generators introduce exercise
上傳時間： 2013-12-16
上傳用戶：2467478207
The Staged Event-Driven Architecture (SEDA) is a new design for building scalable Internet services. SEDA has three major goals: To support massive concurrency, on the order of tens of thousands of clients per node To exhibit robust performance under wide variations in load and, To simplify the design of complex Internet services. SEDA decomposes a complex, event-driven application into a set of stages connected by queues. This design avoids the high overhead associated with thread-based concurrency models, and decouples event and thread scheduling from application logic. SEDA enables services to be well-conditioned to load, preventing resources from being overcommitted when demand exceeds service capacity. Decomposing services into a set of stages also enables modularity and code reuse, as well as the development of debugging tools for complex event-driven applications.
標(biāo)簽： Event-Driven Architecture Internet building
上傳時間： 2015-09-28
上傳用戶：日光微瀾
Delphi for PHP 用戶手冊，英文版，格式PDF。 The IDE User s Guide includes an overview of Delphi for PHP, information on using the IDE, debugging, creating a database application, and a VCL for PHP Component Writer s Guide.
上傳時間： 2015-10-02
上傳用戶：cooran
Magenta Systems Internet Packet Monitoring Components are a set of Delphi components designed to capture and monitor internet packets using either raw sockets or the WinPcap device driver. Hardware permitting, ethernet packets may be captured and interpreted, and statistics maintained about the traffic. Uses of packet monitoring include totalling internet traffic by IP address and service, monitoring external or internal IP addresses and services accessed, network diagnostics, and many other applications. The component includes two demonstration applications, one that displays raw packets, the other that totals internet traffic. The components include various filters to reduce the number of packets that need to be processed, by allowing specific IP addresses to be ignored, LAN mask to ignore local traffic, and ignore non-IP traffic such as ARP.
標(biāo)簽： Components Monitoring components Internet
上傳時間： 2015-10-30
上傳用戶：水中浮云
This document provides guidelines for integrating a discrete high speed USB host controller onto a fourlayer desktop motherboard. The material covered can be broken into three main categories: Board design guidelines, EMI/ESD guidelines and front panel USB guidelines. Section 1.1 Background provides an explanation of the routing experiments and testing performed to validate the feasibility of 480 Megabits per second on an actual motherboard. Section 7 contains a design checklist that lists each design recommendation described in this document. High speed USB operation is described in the USB 2.0 Specification (http://www.usb.org/developers/docs.html).
標(biāo)簽： integrating controller guidelines document
上傳時間： 2013-11-27
上傳用戶：電子世界
This document provides guidelines for integrating a discrete high speed USB host controller onto a fourlayer desktop motherboard. The material covered can be broken into three main categories: Board design guidelines, EMI/ESD guidelines and front panel USB guidelines. Section 1.1 Background provides an explanation of the routing experiments and testing performed to validate the feasibility of 480 Megabits per second on an actual motherboard. Section 7 contains a design checklist that lists each design recommendation described in this document. High speed USB operation is described in the USB 2.0 Specification (http://www.usb.org/developers/docs.html).
標(biāo)簽： integrating controller guidelines document
上傳時間： 2015-11-18
上傳用戶：xhz1993
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