·詳細(xì)說明：用于語音識(shí)別，基于HMM模型，用C++語言編寫?？捎眠B續(xù)語音識(shí)別-It is based on HMM Model and developed with C++ which could be used to continuous speech recognition.
上傳時(shí)間： 2013-05-15
上傳用戶：鳳臨西北
·【英文題名】 Search of Double-fed Machine Variable Speed System Based on DSP 【作者中文名】 沈睿; 【導(dǎo)師】 廖冬初; 【學(xué)位授予單位】 湖北工業(yè)大學(xué); 【學(xué)科專業(yè)名稱】 控制理論與控制工程 【學(xué)位年度】 2007 【論文級(jí)別】 碩士 【網(wǎng)絡(luò)出版投稿人】 湖北工業(yè)大學(xué) 【網(wǎng)絡(luò)出版投稿時(shí)間】 2008-09-27 【關(guān)鍵詞】 雙饋調(diào)速
標(biāo)簽： DSP 雙饋 電機(jī)調(diào)速系統(tǒng)
上傳時(shí)間： 2013-04-24
上傳用戶：hanwu
·關(guān)于機(jī)器人視覺最新的大作，2005最新出版，文件格式為PDF。目前在Amazon上售價(jià)為152美元
標(biāo)簽： nbsp Exploration Video-based Autonomous
上傳時(shí)間： 2013-06-05
上傳用戶：sun_pro12580
·SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL-based design. First, modeling ver
標(biāo)簽： nbsp SystemVerilog Design for
上傳時(shí)間： 2013-07-14
上傳用戶：ainimao
·詳細(xì)說明：該代碼是雙速率的語音壓縮編碼(G.723.1)的matlab代碼。能在matlab6.5以上運(yùn)行-Dual-rate voice compressed encoding(G.723.1) based on MatLab platform. It works on MatLab 6.5 or later versions.
上傳時(shí)間： 2013-06-19
上傳用戶：121212121212
·【英文題名】 Research of Speed Regulate System of Three Phase BLDCM Based on DSP 【作者中文名】 劉桂芬; 【導(dǎo)師】 孟慶春; 【學(xué)位授予單位】 遼寧工程技術(shù)大學(xué); 【學(xué)科專業(yè)名稱】 控制理論與控制工程 【學(xué)位年度】 2007 【論文級(jí)別】 碩士 【網(wǎng)絡(luò)出版投稿人】 遼寧工程技術(shù)大學(xué) 【網(wǎng)絡(luò)出版投稿時(shí)間】 2006-01-02 【
標(biāo)簽： DSP 三相 無刷直流電機(jī) 調(diào)速系統(tǒng)
上傳時(shí)間： 2013-06-19
上傳用戶：leileiq
摘要：本文主要介紹以CPLD 芯片進(jìn)行十字路口的交通燈的設(shè)計(jì)，用CPLD 作為交通燈控制器的主控芯片，采用VHDL\r\n語言編寫控制程序，利用CPLD的可重復(fù)編程和在動(dòng)態(tài)系統(tǒng)重構(gòu)的特性，大大地提高了數(shù)字系統(tǒng)設(shè)計(jì)的靈活性和通用性。\r\n關(guān)鍵詞：CPLD；VHDL；交通燈控制器\r\n中圖分類號(hào)：TP39\r\nAbstract ：This paper introduces the electronic-traffic lamp, which is based on the VHDL and is com
上傳時(shí)間： 2013-08-11
上傳用戶：aesuser
用fpga實(shí)現(xiàn)的DA轉(zhuǎn)換器，有說明和源碼，VDHL文件。\\r\\nA PLD Based Delta-Sigma DAC\\r\\nDelta-Sigma modulation is the simple, yet powerful,\\r\\ntechnique responsible for the extraordinary\\r\\nperformance and low cost of today s audio CD\\r\\nplayers. The simplest Delta-Sigm
標(biāo)簽： fpga DA轉(zhuǎn)換器
上傳時(shí)間： 2013-08-22
上傳用戶：dudu1210004
以圖片的形式簡(jiǎn)單，明了的講解了Proteus中的如何取消TEXT字樣。一看就明白。
標(biāo)簽：
上傳時(shí)間： 2013-09-27
上傳用戶：tiantwo
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時(shí)間： 2014-12-23
上傳用戶：xinhaoshan2016
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