The STi7105 uses state of the art process
technology to provide an ultra low-cost, fully
featured HD AVC decoder IC. It is a highly
integrated system-on-Chip suitable for STB markets across all networks (cable/satellite/DTT/x-
DSL/IP) worldwide
Genode FX is a composition of hardware and software components that enable
the creation of fully fledged graphical user interfaces as system-on-Chip
solutions using commodity FPGAs.
The TAS3204 is a highly-integrated audio system-on-Chip (SOC) consisting of a fully-programmable, 48-bit digital audio processor, a 3:1 stereo analog input MUX, four ADCs, four DACs, and other analog functionality. The TAS3204 is programmable with the graphical PurePath Studio? suite of DSP code development software. PurePath Studio is a highly intuitive, drag-and-drop environment that minimizes software development effort while allowing the end user to utilize the power and flexibility of the TAS3204’s digital audio processing core.
TAS3204 processing capability includes speaker equalization and crossover, volume/bass/treble control, signal mixing/MUXing/splitting, delay compensation, dynamic range compression, and many other basic audio functions. Audio functions such as matrix decoding, stereo widening, surround sound virtualization and psychoacoustic bass boost are also available with either third-party or TI royalty-free algorithms.
The TAS3204 contains a custom-designed, fully-programmable 135-MHz, 48-bit digital audio processor. A 76-bit accumulator ensures that the high precision necessary for quality digital audio is maintained during arithmetic operations.
Four differential 102 dB DNR ADCs and four differential 105 dB DNR DACs ensure that high quality audio is maintained through the whole signal chain as well as increasing robustness against noise sources such as TDMA interference.
The TAS3204 is composed of eight functional blocks:
Clocking System
Digital Audio Interface
Analog Audio Interface
Power supply
Clocks, digital PLL
I2C control interface
8051 MCUcontroller
Audio DSP – digital audio processing
特性
Digital Audio Processor
Fully Programmable With the Graphical, Drag-and-Drop PurePath Studio? Software Development Environment
135-MHz Operation
48-Bit Data Path With 76-Bit Accumulator
Hardware Single-Cycle Multiplier (28 × 48)
數(shù)字化電源的特點：1.控制智能化它是以數(shù)字信號處理器(DSP)或微控制器(MCU)為核心，將數(shù)字電源驅(qū)動器及PWM控制器作為控制對象而構(gòu)成的智能化開關(guān)電源系統(tǒng)。傳統(tǒng)的由微控制器控制的開關(guān)電源，一般只是控制電源的啟動和關(guān)斷，并非真正意義的數(shù)字電源。2.數(shù)模組件組合優(yōu)化采用“整合數(shù)字電源”(Fusion Digital Power)技術(shù)，實現(xiàn)了開關(guān)電源中模擬組件與數(shù)字組件的優(yōu)化組合。例如，功率級所用的模擬組件MOSFET驅(qū)動器，可以很方便地與數(shù)字電源控制器相連并實現(xiàn)各種保護及偏置電源管理，而PWM控制器也屬于數(shù)控模擬芯片。3.集成度高實現(xiàn)了電源系統(tǒng)單片集成化(Power System on Chip)，將大量的分立式元器件整合到一個芯片或一組芯片中。4.控制精度高能充分發(fā)揮數(shù)字信號處理器及微控制器的優(yōu)勢，使所設(shè)計的數(shù)字電源達(dá)到高技術(shù)指標(biāo)。例如，其脈寬調(diào)制(PWM)分辨力可達(dá)150ps(10~12s)的水平，這是傳統(tǒng)開關(guān)電源所望塵莫及的。數(shù)字電源還能實現(xiàn)多相位控制、非線性控制、負(fù)載均流以及故障預(yù)測等功能，為研制綠色節(jié)能型開關(guān)電源提供了便利條件。5.模塊化程度高數(shù)字電源模塊化程度高，各模塊之間可以方便地實現(xiàn)有機融合，便于構(gòu)成分布式數(shù)字電源系統(tǒng)，提高電源系統(tǒng)的可靠性。
Atmel’s AT91SAM7FP105 is a low pincount FingerChip processor based on the 32-bit ARM
RISC processor. It features a on-chip biometric engine performing enrollment verification and
identification, an internal record cache of up to 25 records and a secure command protocol over
USB, SPI, UART. This protocol enables an external host system or processor to control the onchip
bioengine functions, manipulate the record cache, and securely export record cache
records for external storage. Together with the FingerChip sensor device AT77C104B, it forms
an embedded, secured biometric turnkey solution.
The W78E58B is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78E58B is fully compatible with the standard 8052. The
W78E58B contains a 32K bytes of main ROM and a 4K bytes of auxiliary ROM which allows the
contents of the 32KB main ROM to be updated by the loader program located at the 4KB auxiliary
ROM 512 bytes of on-chip RAM four 8-bit bi-directional and bit-addressable I/O ports an additional 4-
bit port P4 three 16-bit timer/counters a serial port. These peripherals are supported by a eight
sources two-level interrupt capability. To facilitate programming and verification, the ROM inside the
W78E58B allows the program memory to be programmed and read electronically. Once the code is
confirmed, the user can protect the code for security
隨著半導(dǎo)體制造技術(shù)不斷的進步，SOC(System On a Chip)是未來IC產(chǎn)業(yè)技術(shù)研究關(guān)注的重點。由于SOC設(shè)計的日趨復(fù)雜化，芯片的面積增大，芯片功能復(fù)雜程度增大，其設(shè)計驗證工作也愈加繁瑣。復(fù)雜ASIC設(shè)計功能驗證已經(jīng)成為整個設(shè)計中最大的瓶頸。 使用FPGA系統(tǒng)對ASIC設(shè)計進行功能驗證，就是利用FPGA器件實現(xiàn)用戶待驗證的IC設(shè)計。利用測試向量或通過真實目標(biāo)系統(tǒng)產(chǎn)生激勵，驗證和測試芯片的邏輯功能。通過使用FPGA系統(tǒng)，可在ASIC設(shè)計的早期，驗證芯片設(shè)計功能，支持硬件、軟件及整個系統(tǒng)的并行開發(fā)，并能檢查硬件和軟件兼容性，同時還可在目標(biāo)系統(tǒng)中同時測試系統(tǒng)中運行的實際軟件。FPGA仿真的突出優(yōu)點是速度快，能夠?qū)崟r仿真用戶設(shè)計所需的對各種輸入激勵。由于一些SOC驗證需要處理大量實時數(shù)據(jù)，而FPGA作為硬件系統(tǒng)，突出優(yōu)點是速度快，實時性好。可以將SOC軟件調(diào)試系統(tǒng)的開發(fā)和ASIC的開發(fā)同時進行。 此設(shè)計以ALTERA公司的FPGA為主體來構(gòu)建驗證系統(tǒng)硬件平臺，在FPGA中通過加入嵌入式軟核處理器NIOS II和定制的JTAG(Joint Test ActionGroup)邏輯來構(gòu)建與PC的調(diào)試驗證數(shù)據(jù)鏈路，并采用定制的JTAG邏輯產(chǎn)生測試向量，通過JTAG控制SOC目標(biāo)系統(tǒng)，達(dá)到對SOC內(nèi)部和其他IP(IntellectualProperty)的在線測試與驗證。同時，該驗證平臺還可以支持SOC目標(biāo)系統(tǒng)后續(xù)軟件的開發(fā)和調(diào)試。 本文介紹了芯片驗證系統(tǒng)，包括系統(tǒng)的性能、組成、功能以及系統(tǒng)的工作原理；搭建了基于JTAG和FPGA的嵌入式SOC驗證系統(tǒng)的硬件平臺，提出了驗證系統(tǒng)的總體設(shè)計方案，重點對驗證系統(tǒng)的數(shù)據(jù)鏈路的實現(xiàn)進行了闡述；詳細(xì)研究了嵌入式軟核處理器NIOS II系統(tǒng)，并將定制的JTAG邏輯與處理器NIOS II相結(jié)合，構(gòu)建出調(diào)試與驗證數(shù)據(jù)鏈路；根據(jù)芯片驗證的要求，設(shè)計出軟核處理器NIOS II系統(tǒng)與PC建立數(shù)據(jù)鏈路的軟件系統(tǒng)，并完成芯片在線測試與驗證。 本課題的整體任務(wù)主要是利用FPGA和定制的JTAG掃描鏈技術(shù)，完成對國產(chǎn)某型DSP芯片的驗證與測試，研究如何構(gòu)建一種通用的SOC芯片驗證平臺，解決SOC驗證系統(tǒng)的可重用性和驗證數(shù)據(jù)發(fā)送、傳輸、采集的實時性、準(zhǔn)確性、可測性問題。本文在SOC驗證系統(tǒng)在芯片驗證與測試應(yīng)用研究領(lǐng)域，有較高的理論和實踐研究價值。
