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system-<b>on-Chip</b>

  • 基于AT89C52單片機(jī)的步進(jìn)電機(jī)控制系統(tǒng)設(shè)計(jì)

    基于AT89C52單片機(jī)的步進(jìn)電機(jī)控制系統(tǒng)設(shè)計(jì) 摘 要: 提出了一個(gè)由AT89C52單片機(jī)控制步進(jìn)電機(jī)的實(shí)例??梢酝ㄟ^(guò)鍵盤輸入相關(guān)數(shù)據(jù), 并根據(jù)需要, 實(shí)時(shí)對(duì)步進(jìn)電機(jī)工作方式進(jìn)行設(shè)置, 具有實(shí)時(shí)性和交互性的特點(diǎn)。該系統(tǒng)可應(yīng)用于步進(jìn)電機(jī)控制的大多數(shù)場(chǎng)合。實(shí)踐表明, 系統(tǒng)性能優(yōu)于傳統(tǒng)的步進(jìn)電機(jī)控制器。 關(guān)鍵詞: 單片機(jī); 步進(jìn)電動(dòng)機(jī); 直流固態(tài)繼電器; 實(shí)時(shí)控制 ABSTRACT: A stepp ing motor control system based on AT89C52 chip microcomputer was described.The data can be inputwith keyboard, and stepp ingmotorwas controlled by these data. According to the demand, users can set the workingmodel of stepp ingmotor in real2time. This system can be widely used in stepp ing motor controlling. The p ractice showed that the performance of this system outdid the tradi-tional stepp ing motor controller.

    標(biāo)簽: 89C C52 AT 89

    上傳時(shí)間: 2013-11-22

    上傳用戶:vodssv

  • 基于8086 CPU 的單芯片計(jì)算機(jī)系統(tǒng)的設(shè)計(jì)

    本文依據(jù)集成電路設(shè)計(jì)方法學(xué),探討了一種基于標(biāo)準(zhǔn)Intel 8086 微處理器的單芯片計(jì)算機(jī)平臺(tái)的架構(gòu)。研究了其與SDRAM,8255 并行接口等外圍IP 的集成,并在對(duì)AMBA協(xié)議和8086 CPU分析的基礎(chǔ)上,采用遵從AMBA傳輸協(xié)議的系統(tǒng)總線代替?zhèn)鹘y(tǒng)的8086 CPU三總線結(jié)構(gòu),搭建了基于8086 IP 軟核的單芯片計(jì)算機(jī)系統(tǒng),并實(shí)現(xiàn)了FPGA 功能演示。關(guān)鍵詞:微處理器; SoC;單芯片計(jì)算機(jī);AMBA 協(xié)議 Design of 8086 CPU Based Computer-on-a-chip System(School of Electrical Engineering and Automation, Heifei University of Technology, Hefei, 230009,China)Abstract: According to the IC design methodology, this paper discusses the design of one kind of Computer-on-a-chip system architecture, which is based on the standard Intel8086 microprocessor,investigates how to integrate the 8086 CPU and peripheral IP such as, SDRAM controller, 8255 PPI etc. Based on the analysis of the standard Intel8086 microprocessor and AMBA Specification,the Computer-on-a-chip system based on 8086 CPU which uses AMBA bus instead of traditional three-bus structure of 8086 CPU is constructed, and the FPGA hardware emulation is fulfilled.Key words: Microprocessor; SoC; Computer-on-a-chip; AMBA Specification

    標(biāo)簽: 8086 CPU 單芯片 計(jì)算機(jī)系統(tǒng)

    上傳時(shí)間: 2013-12-27

    上傳用戶:kernor

  • P90CL301 IIC驅(qū)動(dòng)電路的例行測(cè)試及其程序

    The P90CL301 is a highly integrated 16/32 bit micro-controller especially suitable for applications requiring lowvoltage and low power consumption. It is fully software compatible with the 68000. Furthermore, it provides bothstandard as well as advanced peripheral functions on-chip.One of these peripheral functions is the I2C bus. This report describes worked-out driver software (written in C) toprogram the P90CL301 I2C interface. It also contains interface software routines offering the user a quick start inwriting a complete I2C system application.

    標(biāo)簽: P90 301 IIC 90

    上傳時(shí)間: 2014-01-06

    上傳用戶:氣溫達(dá)上千萬(wàn)的

  • XA-S3的IIC接口的驅(qū)動(dòng)器軟件程序(C語(yǔ)言)

    The XA-S3 is a member of Philips Semiconductors’ XA (eXtended Architecture) family of high performance 16-bit single-chip Microcontrollers. The XA-S3 combines many powerful peripherals on one chip. Therefore, it is suited for general multipurpose high performance embedded control functions.One of the on-chip peripherals is the I2C bus interface. This report describes worked-out driver software (written in C) to program / use the I2C interface of the XA-S3. The driver software, together with a demo program and interface software routines offer the user a quick start in writing a complete I2C - XAS3 system application.

    標(biāo)簽: XA-S IIC C語(yǔ)言 接口

    上傳時(shí)間: 2013-11-10

    上傳用戶:liaofamous

  • at89c52 pdf

    The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard 80C51 and 80C52 instruction set and pinout.The on-chip Flash allows the program memory to be reprogrammed in-system or by aconventional nonvolatile memory programmer. By combining a versatile 8-bit CPUwith Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputerwhich provides a highly-flexible and cost-effective solution to many embedded controlapplications.

    標(biāo)簽: 89c c52 at

    上傳時(shí)間: 2013-11-10

    上傳用戶:1427796291

  • LPC1850 Cortex-M3內(nèi)核微控制器數(shù)據(jù)手冊(cè)

    The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.

    標(biāo)簽: Cortex-M 1850 LPC 內(nèi)核微控制器

    上傳時(shí)間: 2014-12-31

    上傳用戶:zhuoying119

  • LPC1300系列產(chǎn)品勘誤數(shù)據(jù)手冊(cè)

    On the LPC13xx, programming, erasure and re-programming of the on-chip flash can be performed using In-System Programming (ISP) via the UART serial port, and also, can be performed using In-Application Programming (IAP) calls directed by the end-user code. For In-System Programming (ISP) via the UART serial port, the ISP command handler (resides in the bootloader) allows erasure of one or more sector (s) of the on-chip flash memory.

    標(biāo)簽: 1300 LPC 勘誤 數(shù)據(jù)手冊(cè)

    上傳時(shí)間: 2013-12-13

    上傳用戶:lmq0059

  • 賽靈思電機(jī)控制開(kāi)發(fā)套件簡(jiǎn)介(英文版)

      The power of programmability gives industrial automation designers a highly efficient, cost-effective alternative to traditional motor control units (MCUs)。 The parallel-processing power, fast computational speeds, and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control (FOC)。   Additionally, Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing (DSP) that can tackle compute-intensive functions such as PID Controller, Clark/Park transforms, and Space Vector PWM.   The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving, proven, motor-control reference designs. The kit also shortens the process of developing custom control capabilities, with integrated peripheral functions (Ethernet, PowerLink, and PCI® Express), a motor-control FPGA mezzanine card (FMC) with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators, and prototyping support for evaluating alternative front-end circuitry.

    標(biāo)簽: 賽靈思 電機(jī)控制 開(kāi)發(fā)套件 英文

    上傳時(shí)間: 2013-10-28

    上傳用戶:wujijunshi

  • 介紹幾種cpuThe 8xC251SA/SB/SP/SQ improves on the MCS-51 architecture and peripheral features, introducin

    介紹幾種cpuThe 8xC251SA/SB/SP/SQ improves on the MCS-51 architecture and peripheral features, introducing the advanced register based CPU architecture i.e., the MCS 251 microcontroller architecture. The register based CPU supports a 40-byte register file. In addition, the 8xC251SA/SB/SP/SQ microcontroller has 256-Kbyte expanded external code/data memory space and 64-Kbyte stack space. The new controller is also specially designed to execute C code efficiently. More importantly, the 8xC251SA/SB/SP/SQ maintains binary code compatibility with MCS 51 microcontrollers but at the same time allows the use of the powerful MCS 251 microcontroller instruction set, with many new 8, 16 and 32 bit instructions available. The 8xC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip data RAM options and is available in 16 Kbytes and 8 Kbytes of on-chip ROM/OTPROM or ROMless options.

    標(biāo)簽: architecture introducin peripheral improves

    上傳時(shí)間: 2015-03-15

    上傳用戶:ccclll

  • A book describle in detail about the system security and usability technology. It is a system book o

    A book describle in detail about the system security and usability technology. It is a system book on security.

    標(biāo)簽: system book technology describle

    上傳時(shí)間: 2015-07-22

    上傳用戶:zmy123

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