TCS ECN Background & Key TermsTrust Issues with PCIe PlatformsTCS ECN DetailsTrusted Config Space and TCS TransactionsTrusted Config Access Mech (TCAM)Standard vs Trusted Config AccessNew Capability StructuresTCS Support in Root Ports, Switches, & BridgesTCS “Does not…” ListExample Trusted Computing PlatformRevisiting the Trust IssuesKey Takeaways/Call to ActionQuestions
標(biāo)簽： Configuration Trusted PCIe Spa
上傳時(shí)間： 2013-11-21
上傳用戶：hsfei8
[PIC項(xiàng)目實(shí)戰(zhàn)：基于PIC18].Advanced.PIC.Microcontroller.Projects.in.C
標(biāo)簽： PIC Microcontroller Advanced Projects
上傳時(shí)間： 2013-11-21
上傳用戶：二驅(qū)蚊器
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
標(biāo)簽： Signal Input Fall Rise
上傳時(shí)間： 2013-10-23
上傳用戶：copu
什么是JTAG 到底什么是JTAG呢？ JTAG(Joint Test Action Group)聯(lián)合測(cè)試行動(dòng)小組)是一種國(guó)際標(biāo)準(zhǔn)測(cè)試協(xié)議（IEEE 1149.1兼容），主要用于芯片內(nèi)部測(cè)試。現(xiàn)在多數(shù)的高級(jí)器件都支持JTAG協(xié)議，如DSP、FPGA器件等。標(biāo)準(zhǔn)的JTAG接口是4線：TMS、 TCK、TDI、TDO，分別為模式選擇、時(shí)鐘、數(shù)據(jù)輸入和數(shù)據(jù)輸出線。 JTAG最初是用來(lái)對(duì)芯片進(jìn)行測(cè)試的，基本原理是在器件內(nèi)部定義一個(gè)TAP（Test Access Port�測(cè)試訪問(wèn)口）通過(guò)專用的JTAG測(cè)試工具對(duì)進(jìn)行內(nèi)部節(jié)點(diǎn)進(jìn)行測(cè)試。JTAG測(cè)試允許多個(gè)器件通過(guò)JTAG接口串聯(lián)在一起，形成一個(gè)JTAG鏈，能實(shí)現(xiàn)對(duì)各個(gè)器件分別測(cè)試。現(xiàn)在，JTAG接口還常用于實(shí)現(xiàn)ISP（In-System rogrammable�在線編程），對(duì)FLASH等器件進(jìn)行編程。 JTAG編程方式是在線編程，傳統(tǒng)生產(chǎn)流程中先對(duì)芯片進(jìn)行預(yù)編程現(xiàn)再裝到板上因此而改變，簡(jiǎn)化的流程為先固定器件到電路板上，再用JTAG編程，從而大大加快工程進(jìn)度。JTAG接口可對(duì)PSD芯片內(nèi)部的所有部件進(jìn)行編程 JTAG的一些說(shuō)明 通常所說(shuō)的JTAG大致分兩類，一類用于測(cè)試芯片的電氣特性，檢測(cè)芯片是否有問(wèn)題；一類用于Debug；一般支持JTAG的CPU內(nèi)都包含了這兩個(gè)模塊。 一個(gè)含有JTAG Debug接口模塊的CPU，只要時(shí)鐘正常，就可以通過(guò)JTAG接口訪問(wèn)CPU的內(nèi)部寄存器和掛在CPU總線上的設(shè)備，如FLASH，RAM，SOC（比如4510B，44Box，AT91M系列）內(nèi)置模塊的寄存器，象UART，Timers，GPIO等等的寄存器。 上面說(shuō)的只是JTAG接口所具備的能力，要使用這些功能，還需要軟件的配合，具體實(shí)現(xiàn)的功能則由具體的軟件決定。 例如下載程序到RAM功能。了解SOC的都知道，要使用外接的RAM，需要參照SOC DataSheet的寄存器說(shuō)明，設(shè)置RAM的基地址，總線寬度，訪問(wèn)速度等等。有的SOC則還需要Remap，才能正常工作。運(yùn)行Firmware時(shí)，這些設(shè)置由Firmware的初始化程序完成。但如果使用JTAG接口，相關(guān)的寄存器可能還處在上電值，甚至?xí)r錯(cuò)誤值，RAM不能正常工作，所以下載必然要失敗。要正常使用，先要想辦法設(shè)置RAM。在ADW中，可以在Console窗口通過(guò)Let 命令設(shè)置，在AXD中可以在Console窗口通過(guò)Set命令設(shè)置。
上傳時(shí)間： 2013-10-23
上傳用戶：aeiouetla
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
標(biāo)簽： Base-Station Applications Single-Chip Transceiver
上傳時(shí)間： 2013-11-07
上傳用戶：songrui
針對(duì)高校實(shí)驗(yàn)教學(xué)的現(xiàn)狀以及存在的問(wèn)題，提出了基于Struts的網(wǎng)絡(luò)實(shí)驗(yàn)教學(xué)平臺(tái)。設(shè)計(jì)這樣一個(gè)教學(xué)平臺(tái)其主要目的也是在幫助學(xué)生完成對(duì)知識(shí)的建構(gòu)，同時(shí)也必需要考慮相應(yīng)的教學(xué)目標(biāo)以及教學(xué)策略的運(yùn)用。該平臺(tái)采用C/S局域網(wǎng)，把實(shí)驗(yàn)教學(xué)系統(tǒng)放在服務(wù)器端，讓學(xué)生通過(guò)瀏覽器來(lái)訪問(wèn)，軟件使用MVC模式。平臺(tái)整合了現(xiàn)有的實(shí)驗(yàn)資源，通過(guò)實(shí)驗(yàn)預(yù)約排課等模塊輔助實(shí)驗(yàn)室管理員的日常管理工作，幫助實(shí)驗(yàn)教學(xué)順利有效的開(kāi)展，實(shí)現(xiàn)學(xué)生的個(gè)性化學(xué)習(xí)，實(shí)現(xiàn)以人為本的教育理念；同時(shí)促進(jìn)了教育信息化的發(fā)展，有利于培養(yǎng)學(xué)生的綜合素質(zhì)。
標(biāo)簽： Struts 網(wǎng)絡(luò) 實(shí)驗(yàn) 教學(xué)平臺(tái)
上傳時(shí)間： 2013-11-10
上傳用戶：zczc
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
標(biāo)簽： Base-Station Applications Single-Chip Transceiver
上傳時(shí)間： 2013-11-05
上傳用戶：超凡大師
本程序集是Allen I. Holub所寫的《Compiler Design in C》一書(shū)的附隨軟件，其中有作者自己編寫的詞法分析和語(yǔ)法分析工具LeX，occs和LLama，該軟件包還包括一個(gè)顯示C語(yǔ)言分析過(guò)程的程序
標(biāo)簽： I. Compiler Design Allen
上傳時(shí)間： 2014-01-08
上傳用戶：siguazgb
PGP Components使用PGP算法的加密控件。(有源代碼）工作在：D2 D3 D4 D5。作者：Michael in der Wiesche
標(biāo)簽： Components PGP Michael Wiesche
上傳時(shí)間： 2013-12-28
上傳用戶：koulian
a set of cross-platform tools that is useful for programming the GBA written in Java.
標(biāo)簽： cross-platform programming written useful
上傳時(shí)間： 2015-01-06
上傳用戶：yd19890720
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
