介紹了基于單片機航空交流電參數測試儀的系統設計。以Silicon Labs公司的C8051F005單片機為核心設計出數據采集板，通過RS-232串口與上位機通訊。運用Lab Windows/CVI編寫的上位機軟件實現信號的檢測以及波形和數據的顯示，給出了測試儀硬件電路的組成和軟件流程圖。本系統具有硬件結構簡單、容易實現和成本低等特點，在實際應用中其穩定性、精確性均能滿足客戶要求。 Abstract: The design of aeronautics AC parameters tester based on the single-chip is introduced.The core component of data acquisition board is C8051F005 single chip of Silicon Labs Company,and communication with PC through RS-232. The signal processing software programmed with LabWindows/CVI can be used successfully to fulfill inspection of signal and display of the waveform and data. The hardware and software configuration of test instrument are provided.The hardware of the system is simple, and can be easily realized.The stability and precision of the measurement instrument are enough to meet the requirements.
上傳時間： 2013-11-18
上傳用戶：wang5829
隨著單片機功能集成化的發展，其應用領域也逐漸地由傳統的控制，擴展為控制處理、數據處理以及數字信號處理（DSP，Digital Signal Processing）等領域。凌陽的16位單片機就是為適應這種發展而設計的。它的CPU內核采用凌陽最新推出的µ’nSP™（Microcontroller and Signal Processor）16位微處理器芯片（以下簡稱µ’nSP™）。圍繞µ’nSP™所形成的16位µ’nSP™系列單片機（以下簡稱µ’nSP™家族）采用的是模塊式集成結構，它以µ’nSP™內核為中心集成不同規模的ROM、RAM和功能豐富的各種外設接口部件。
上傳時間： 2013-11-07
上傳用戶：wpwpwlxwlx
This application note describes how to decode standard DTMF tones using the minimum number of external discrete components and a PIC. The two examples use a PIC which has an 8 bit timer and either a comparator or an ADC, although it can be modified for use on a PIC which has only digital I/O. The Appendices have example code for the 16C662 (with comparator) and 16F877 (using the ADC). As the majority of the Digital Signal Processing is done in software, little is required in the way of external signal conditioning. Software techniques are used to model the individual elements of a DTMF Decoder IC.
上傳時間： 2013-11-21
上傳用戶：zhaoke2005
SPCE061A采用的內核 SPCE061A采用的內核（CPU）為μ‘nSP。 μ‘nSP（讀做micro-n-S-P）是凌陽科技推出的16位微處理器，它的突出特點是較高的處理速度，這就使其有能力進行復雜的數字信號處理（DSP，Digital Signal Processing）。 μ‘nSP內核由凌陽自主開發，因而也具備它自己的指令系統。 指令系統.61 3.1 指令系統的概述及符號約定.61 3.2 數據傳送指令62 3.3 算術運算..66 3.3.1 加法運算..67 3.3.2 減法運算..68 3.3.3 帶進位的加減運算.70 3.3.4 取補運算..70 3.3.5 SPCE061A的乘法指令.71 3.3.6 SPCE061A的n項內積運算指令.71 3.3.7 比較運算(影響標志位N,Z,S,C)..73 3.4 SPCE061A的邏輯運算.74 3.4.1 邏輯與..74 3.4.2 邏輯或..75 3.4.3 邏輯異或..76 3.4.4 測試（TEST）.78 3.4.5 SPCE061A的移位操作.80 3.5 SPCE061A的控制轉移類指令..83 3.6 偽指令86 3.6.1 偽指令的語法格式及特點..87 3.6.2 偽指令符號約定..87 3.6.3 標準偽指令.87 3.6.4 宏定義與調用98 3.6.5 段的定義與調用101 3.6.6 結構的定義與調用..102 3.6.7 過程的定義與調用..106 3.6.8 偽指令的應用舉例..106
上傳時間： 2013-10-31
上傳用戶：xuanchangri
With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
上傳時間： 2013-11-07
上傳用戶：swing
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上傳時間： 2013-10-28
上傳用戶：15501536189
Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上傳時間： 2013-10-12
上傳用戶：kang1923
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
上傳時間： 2013-10-28
上傳用戶：wujijunshi
Mobile phones are constantly decreasing in size, thereby complicating the acoustical functionality. Signal processing methods can be used to partially mitigate this problem. In this paper we suggest a method which uses multiple spectral subtraction functions and two microphones, introducing only a short signal delay.
標簽： functionality complicating acoustical constantly
上傳時間： 2015-11-15
上傳用戶：youth25
The data files included are .MAT or *.dat (ASCII)files. The m-files and the data may be distributed, provided that the source is acknowledged in any publication and the data are not sold. Since this software is being distributed free of charge, the authors are not offering any technical support. Students who have any questions or difficulties using this software, or require the additional functions from the Signal Processing Toolbox should contact their professor.
標簽： files data distributed The
上傳時間： 2014-12-06
上傳用戶：wuyuying
