本文檔是汽車單線通訊SENT協(xié)議2010年標(biāo)準(zhǔn)資料。
標(biāo)簽： sent協(xié)議 汽車通訊
上傳時(shí)間： 2022-07-22
上傳用戶：fliang
最強(qiáng)勁的PDF工具Adobe Acrobat XI Pro 11（Acrobat reader）終于與大家見面了！它已經(jīng)不僅只是出色的PDF編輯、轉(zhuǎn)換軟件。此次更新深度整合了Microsoft Office套件，實(shí)現(xiàn)了PDF與Word、Excel以及PowerPoint等文檔間的無縫相互轉(zhuǎn)換，并整合了云服務(wù)，你可以將PDF文檔存儲(chǔ)在微軟SharePoint服務(wù)器和Office 365之上，也可以存儲(chǔ)在 Adobe自家的Acrobat.com云端服務(wù)器中。而且Adobe Acrobat XI Pro將完美支持IOS、Andriod和Wondows8平臺(tái)。
上傳時(shí)間： 2013-06-27
上傳用戶：eeworm
英飛凌科技股份公司近日推出適用于汽車動(dòng)力總成和底盤應(yīng)用的全新AUDO MAX系列32位微控制器。AUDO MAX系列可為發(fā)動(dòng)機(jī)管理系統(tǒng)滿足歐5和歐6排放標(biāo)準(zhǔn)提供支持，使電動(dòng)汽車的動(dòng)力總成功能實(shí)現(xiàn)電氣化。AUDO MAX系列的主要特性包括：高達(dá)300MHz的最大時(shí)鐘頻率、SENT和FlexRay?等高速接口以及利用PRO-SIL?特性為先進(jìn)安全設(shè)計(jì)提供全面支持。此外，這種全新的微控制器適用于在高達(dá)170°C*的溫度條件下使用。AUDO MAX系列以TriCore?處理器架構(gòu)為基礎(chǔ)，采用90納米工藝制造。
標(biāo)簽： Fairchild
上傳時(shí)間： 2013-05-24
上傳用戶：CHINA526
耿國華FLASH課件 供大家分享 謝謝 -jie yong bei ren de dong xi jiushi xiang xia zai yi xie dong xi
標(biāo)簽： AltovaXMLSpy 2006
上傳時(shí)間： 2013-07-13
上傳用戶：qazxsw
PCB Layout Rule Rev1.70, 規(guī)範(fàn)內(nèi)容如附件所示, 其中分為: (1) ”PCB LAYOUT 基本規(guī)範(fàn)”:為R&D Layout時(shí)必須遵守的事項(xiàng), 否則SMT,DIP,裁板時(shí)無法生產(chǎn). (2) “錫偷LAYOUT RULE建議規(guī)範(fàn)”: 加適合的錫偷可降低短路及錫球. (3) “PCB LAYOUT 建議規(guī)範(fàn)”:為製造單位為提高量產(chǎn)良率,建議R&D在design階段即加入PCB Layout. (4) ”零件選用建議規(guī)範(fàn)”: Connector零件在未來應(yīng)用逐漸廣泛, 又是SMT生產(chǎn)時(shí)是偏移及置件不良的主因,故製造希望R&D及採購在購買異形零件時(shí)能顧慮製造的需求, 提高自動(dòng)置件的比例.
標(biāo)簽： LAYOUT PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2013-10-28
上傳用戶：zhtzht
針對目前使用的RS232接口數(shù)字化B超鍵盤存在PC主機(jī)啟動(dòng)時(shí)不能設(shè)置BIOS，提出一種PS2鍵盤的設(shè)計(jì)方法。基于W78E052D單片機(jī)，采用8通道串行A/D轉(zhuǎn)換器設(shè)計(jì)了8個(gè)TGC電位器信息采集電路，電位器位置信息以鍵盤掃描碼序列形式發(fā)送，正交編碼器信號(hào)通過XC9536XL轉(zhuǎn)換為單片機(jī)可接收的中斷信號(hào)，軟件接收到中斷信息后等效處理成按鍵。結(jié)果表明，在滿足開機(jī)可設(shè)置BIOS同時(shí)，又可實(shí)現(xiàn)超聲特有功能，不需要專門設(shè)計(jì)驅(qū)動(dòng)程序，接口簡單，成本低。 Abstract: Aiming at the problem of the digital ultrasonic diagnostic imaging system keyboard with RS232 interface currently used couldn?蒺t set the BIOS when the PC boot， this paper proposed a design method of PS2 keyboards. Based on W78E052D microcontroller，designed eight TGC potentiometers information acquisition circuit with 8-channel serial A/D converter， potentiometer position information sent out with keyboard scan code sequentially.The control circuit based on XC9536 CPLD is used for converting the mechanical actions of the encoders into the signals that can be identified by the MCU， software received interrupt information and equivalently treatmented as key. The results show that the BIOS can be set to meet the boot， ultrasound specific functionality can be achieved at the same time， it does not require specially designed driver，the interface is simple and low cost.
標(biāo)簽： 單片機(jī) B超 數(shù)字化 鍵盤設(shè)計(jì)
上傳時(shí)間： 2013-10-10
上傳用戶：asdfasdfd
以C8051F020為核心處理器，設(shè)計(jì)無線傳感器網(wǎng)絡(luò)數(shù)據(jù)采集系統(tǒng)。系統(tǒng)采用SZ05-ADV型無線通訊模塊組建Zigbee無線網(wǎng)絡(luò)，結(jié)合嵌入式系統(tǒng)的軟硬件技術(shù)，完成終端節(jié)點(diǎn)的8路傳感器信號(hào)的數(shù)據(jù)采集。現(xiàn)場8路信號(hào)通過前端處理后，分別送入C8051F020的12位A/D轉(zhuǎn)換器進(jìn)行轉(zhuǎn)換。經(jīng)過精確處理、存儲(chǔ)后的現(xiàn)場數(shù)據(jù)，通過Zigbee無線網(wǎng)絡(luò)傳送到上位機(jī)，系統(tǒng)可達(dá)到汽車試驗(yàn)中無線測試的目的。 Abstract: This paper designs a wireless sensor network system for data acquisition with C8051F020 as core processors.The system used SZ05-ADV wireless communication module，set up a Zigbee wireless network， combined with hardware and software technologies of embedded systems，completed the end-node 8-locale sensor signal data acquisition.Eight locale signals were sent separately into the 12-bit ADC of C8051F020 for conversion through front treatment.After accurate processing and storage，the locale data was transmitted to the host computer through Zigbee wireless.The system achieves the purpose of wireless testing in vehicle trial.
標(biāo)簽： C8051F020 Zigbee 汽車測試 系統(tǒng)設(shè)計(jì)
上傳時(shí)間： 2013-11-23
上傳用戶：dsgkjgkjg
介紹一種簡單射頻識(shí)別系統(tǒng)設(shè)計(jì)。該設(shè)計(jì)包括閱讀器、應(yīng)答器和線圈3部分。由單片機(jī)控制閱讀器向應(yīng)答器發(fā)射無線信號(hào)，并接收應(yīng)答器回送的信號(hào)，再通過分析回送信號(hào)識(shí)別物品。閱讀器和應(yīng)答器之間以半雙工通信方式通信。 Abstract: A simple design of radio frequency identification system is given in this paper.The design includes reader,responder and winding.Through MCU，signals are sent to responder from reader，then corresponding signals are sent back. According to the analysis of the signals sent back，the objects can be identified.Half-duplex communication is adopted? between? reader? and? responder.
標(biāo)簽： 51單片機(jī) 無線識(shí)別 裝置
上傳時(shí)間： 2013-10-11
上傳用戶：plsee
The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices if the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the slave devices on the downstream I2C-bus.
標(biāo)簽： master C-bus 9541 PCA
上傳時(shí)間： 2013-10-09
上傳用戶：3294322651
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-14
上傳用戶：fdmpy
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