使用Nios II緊耦合存儲器教程 Chapter 1. Using Tightly Coupled Memory with the Nios II Processor Reasons for Using Tightly Coupled Memory . . . . . . . . . . . . . . . . . . . . . . . 1–1 Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Guidelines for Using Tightly Coupled Memory . . . .. . . . . . . . 1–2 Hardware Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Software Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 1–3 Locating Functions in Tightly Coupled Memory . . . . . . . . . . . . . 1–3 Tightly Coupled Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Dual Port Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 1–5 Building a Nios II System with Tightly Coupled Memory . . . . . . . . . . . 1–5
上傳時間： 2013-10-13
上傳用戶：黃婷婷思密達
Nios II 軟件開發人員手冊中的緩存和緊耦合存儲器部分 Nios® II embedded processor cores can contain instruction and data caches. This chapter discusses cache-related issues that you need to consider to guarantee that your program executes correctly on the Nios II processor. Fortunately, most software based on the Nios II hardware abstraction layer (HAL) works correctly without any special accommodations for caches. However, some software must manage the cache directly. For code that needs direct control over the cache, the Nios II architecture provides facilities to perform the following actions:
上傳時間： 2013-10-25
上傳用戶：蟲蟲蟲蟲蟲蟲
Nios II 系列處理器配置選項:This chapter describes the Nios® II Processor parameter editor in Qsys and SOPC Builder. The Nios II Processor parameter editor allows you to specify the processor features for a particular Nios II hardware system. This chapter covers the features of the Nios II processor that you can configure with the Nios II Processor parameter editor; it is not a user guide for creating complete Nios II processor systems.
上傳時間： 2015-01-01
上傳用戶：mahone
Nios II內核詳細實現
上傳時間： 2015-01-01
上傳用戶：源碼3
本文采用Altera公司的FPGA器件Cyclone III系列EP3C10作為核心器件構成了R-S（255，223）編碼系統；利用Quartus II 9.0作為硬件仿真平臺，用硬件描述語言Verilog_HDL實現編程，并且通過JTAG接口與EP3C10連接。R-S（Reed-Solomon）碼是一類糾錯能力很強的特殊的非二進制BCH碼，能應對隨機性和突發性錯誤，廣泛應用于各種通信系統中和保密系統中。R-S（255，223）碼能夠檢測32字節長度和糾錯16字節長度的連續數據錯誤信息。
標簽： CycloneIII RS編碼
上傳時間： 2013-10-08
上傳用戶：yuchunhai1990
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
標簽： CoolRunner-II XAPP CPLD 380
上傳時間： 2013-10-26
上傳用戶：kiklkook
This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can be expanded by the user to perform additional operations usingthe remaining CPLD resources
標簽： CoolRunner-II Xilinx XAPP CPLD
上傳時間： 2013-12-16
上傳用戶：qwer0574
東南大學綜合電子實踐Quartus ii課程設計報告 包含跑馬燈，數字鐘和交通燈設計
上傳時間： 2015-01-02
上傳用戶：超凡大師
There are many manufacturers of dot matrix LCD modules. However, most of these displaysare similar. They all have on-board controllers and drivers capable of displaying alpha numericsand a wide variety of other symbols (including Japanese "Katakana" characters). The internaloperation of LCD controller devices is determined by signals sent from a central processing unit(in this case, a CoolRunner-II CPLD).
標簽： CoolRunner-II XAPP 904 LCD
上傳時間： 2013-12-17
上傳用戶：haiya2000
16kb/s Low Delay CELP 算法
上傳時間： 2015-01-03
上傳用戶：huangld
