針對船舶氣象儀保障維修而設計的船舶氣象儀測試系統，包括信息處理終端、主儀器檢測模塊、傳感器檢測模塊，各個模塊都采用基于AVR單片機的嵌入式系統，模塊之間通過CAN總線進行通信。結果表明，船舶氣象儀測試系統能夠快速檢測船舶氣象儀故障，與單純依靠人工方式排查故障相比，故障檢測時間縮短了60%以上。 Abstract: The test system of ship meteorological instrument was developed to satisfy the maintenance of ship meteorological instruments，which composed of information processing terminal， testing module of main instrument and testing module of sensors. Each of these modules included an embedded system based on microcontroller of AVR series and communicated with other module by CAN bus. The results show that the test system can judge the fault of ship meteorological instrument quickly and shorten the fault detection time as much as 60% compared with simple manual troubleshooting.
上傳時間： 2013-11-23
上傳用戶：stvnash
1 FEATURES· Single chip LCD controller/driver· 1 or 2-line display of up to 24 characters per line, or2 or 4 lines of up to 12 characters per line· 5 ′ 7 character format plus cursor; 5 ′ 8 for kana(Japanese syllabary) and user defined symbols· On-chip:– generation of LCD supply voltage (external supplyalso possible)– generation of intermediate LCD bias voltages– oscillator requires no external components (externalclock also possible)· Display data RAM: 80 characters· Character generator ROM: 240 characters· Character generator RAM: 16 characters· 4 or 8-bit parallel bus or 2-wire I2C-bus interface· CMOS/TTL compatible· 32 row, 60 column outputs· MUX rates 1 : 32 and 1 : 16· Uses common 11 code instruction set· Logic supply voltage range, VDD - VSS: 2.5 to 6 V· Display supply voltage range, VDD - VLCD: 3.5 to 9 V· Low power consumption· I2C-bus address: 011101 SA0.
上傳時間： 2013-11-08
上傳用戶：laozhanshi111
FEATURES400 MSPS internal clock speedIntegrated 10-bit DAC32-bit tuning wordPhase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)Excellent dynamic performance>75 dB SFDR @ 160 MHz (±100 kHz offset) AOUTSerial I/O control1.8 V power supplySoftware and hardware controlled power-down48-lead TQFP/EP packageSupport for 5 V input levels on most digital inputsPLL REFCLK multiplier (4× to 20×)Internal oscillator; can be driven by a single crystalPhase modulation capabilityMultichip synchronization
上傳時間： 2014-12-04
上傳用戶：axin881314
因為工作的緣故，必須學習EMC單片機了。我會把我的學習歷程寫下來，算是對壇子的一點貢獻，也算是自己的一個總結吧。因為以前學過51的和PIC、HOLTEK的單片機，并且也大致了解過EMC的指令集，所以學起來并不是太難。為了學習，而又沒有仿真器，于是去emc的網站下載了一個simulator來軟件仿真。第一感覺還不錯，把里面的例子程序跑了一下，單步執行然后看寄存器的變化。發現他的IDE環境不是特別好用，首先編輯器無法設置TAB的寬度，導致UE里面寫好的代碼，都不整齊了。再說一下對EMC指令集的理解。EMC的寄存器占用2個空間：內存空間和IO空間，前者用mov來訪問，后者用IOW和IOR等來訪問。這點我想很多初學者都會象我一樣，要花點時間來理解這個問題。還有就是很多寄存器沒有地址的，也就是占用特殊的地址空間，既不是內存也不是IO空間，比如CONT等。我想，正是這種類繁多的尋址，使得在簡單的MCU上可以2個clock跑一條單周期指令。對于此，PIC和HOLTEK的單片機都需要4個clock跑一條單周期指令，51系列CISC指令就更不用說了。
上傳時間： 2013-11-05
上傳用戶：龍飛艇
Features• Complete DTMF Receiver• Low power consumption• Internal gain setting amplifier• Adjustable guard time• Central office quality• Power-down mode• Inhibit mode• Backward compatible withMT8870C/MT8870C-1Applications• Receiver system for British Telecom (BT) orCEPT Spec (MT8870D-1)• Paging systems• Repeater systems/mobile radio• Credit card systems• Remote control• Personal computers• Telephone answering machine
上傳時間： 2013-11-20
上傳用戶：mpquest
The PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
上傳時間： 2013-11-17
上傳用戶：vodssv
Virtex-5, Spartan-DSP FPGAs Application Note This application note demonstrates how efficient implementations of Digital Up Converters(DUC) and Digital Down Converters (DDC) can be done by leveraging the Xilinx DSP IPportfolio for increased productivity and reduced time to development. Step-by-step instruction is given on how to perform system-level trade off analysis and develop the most efficient FPGA implementation, thus allowing engineers a flexible, low-cost and low-power alternative to ASSP technologies.
標簽： Spartan-DSP Virtex FPGAs Ap
上傳時間： 2013-10-23
上傳用戶：raron1989
The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAT25128 device. The device featuressoftware and hardware write protection, including partial as well as full array protection.
上傳時間： 2013-11-15
上傳用戶：fklinran
FeaturesThe following standard features are provided.• Choice of RTOS scheduling policy1. Pre-emptive:Always runs the highest available task. Tasks of identical priorityshare CPU time (fully pre-emptive with round robin time slicing).2. Cooperative:Context switches only occur if a task blocks, or explicitly callstaskYIELD().• Co-routines (light weight tasks that utilise very little RAM).• Message queues• Semaphores [via macros]• Trace visualisation ability (requires more RAM)• Majority of source code common to all supported development tools• Wide range of ports and examples
上傳時間： 2013-10-13
上傳用戶：13162218709
匯編器在微處理器的驗證和應用中舉足輕重，如何設計通用的匯編器一直是研究的熱點之一。本文提出了一種開放式的匯編器系統設計思想，在匯編語言與機器語言間插入中間代碼CMDL（code mapping description language）語言，打破匯編語言與機器語言的直接映射關系，由此建立起一套描述匯編語言與機器語言的開放式映射體系。基于此開放式映射體系開發了一套匯編器系統，具有較高層次上的通用性和可移植性。【關鍵詞】指令集，CMDL，匯編器，開放式 Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【關鍵詞】instruction set, symbol table, assembler, lexical analysis, retargetability
上傳時間： 2013-10-10
上傳用戶：meiguiweishi
