the PCB of USB2LPT,ready to use
上傳時間： 2013-12-08
上傳用戶：徐孺
Matlab NLMS program, ready for using
標簽： program Matlab ready using
上傳時間： 2014-08-23
上傳用戶：離殤
s12（x）s 系列 BDM 制作原理圖及相關驅動 s12 (x) s series BDM production and related drive schematic
標簽： production s12 BDM schematic
上傳時間： 2013-12-21
上傳用戶：小寶愛考拉
51單片機的下載線制作原理及圖,下載軟件和下載的全過程51 single-chip production lines of principle and download maps, download software and download the entire process of
標簽： download single-chip production principle
上傳時間： 2017-08-10
上傳用戶：waitingfy
SPI Control Module ready Code
上傳時間： 2014-01-21
上傳用戶：xuan‘nian
例題iIt s time to wake up! It s time to get out of bed. It s time to get ready.
上傳時間： 2014-01-10
上傳用戶：gtf1207
This is the Ready project caller Id based on the Atmel Chip 8051... PCB layout is also given in this file
上傳時間： 2017-08-29
上傳用戶：杜瑩12345
Main program running when workpiece is ready on deferent belt(deferent_ready=ture). * Call Square_Wave subroutine to generate 0.5ms square wave on P1.2 to drive * electromotor,then drive deferent belt step forward. When it steps to the measure * zone, it stops to be measured. Then call A_D subroutine to transform analog * signals to digital signals , after then call serial subroutine to transfer * digital signals to PC. Call square wave subroutine to drive deferent belt step to * original position waitting for defere ready flag to run the next circle.
標簽： deferent_ready workpiece deferent program
上傳時間： 2017-08-31
上傳用戶：baiom
最新生產中的MT6226工廠成品版PCB文件下載-The latest production version of the MT6226 factory finished PCB File Downl
上傳時間： 2013-07-30
上傳用戶：gonuiln
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上傳時間： 2014-12-23
上傳用戶：xinhaoshan2016
