文中在pre-FFT定時同步算法的基礎(chǔ)上提出一個新的定時同步算法及其改進(jìn)算法，該算法利用規(guī)則集對相關(guān)函數(shù)和導(dǎo)函數(shù)優(yōu)化的方法得以進(jìn)一步減小估計方差，本文在給出其推導(dǎo)過程的基礎(chǔ)上給出了仿真結(jié)果，并與相關(guān)算法進(jìn)行比較，結(jié)果表明新算法的定時估計精度較高且具有一定的魯棒性。
上傳時間： 2013-10-29
上傳用戶：hebmuljb
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上傳時間： 2013-10-28
上傳用戶：15501536189
Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.
上傳時間： 2013-10-30
上傳用戶：ysjing
摘要：介紹了基于數(shù)字信號處理(Digital Signal Processor,DSP)的運動控制器GT-800在貼片機控制系統(tǒng)中的應(yīng)用。該系統(tǒng)采用以PC機為上位機、GT-800運動控制器為下位機的硬件結(jié)構(gòu)，上下位機之間的通訊采用基于ISA總線的雙端口RAM的模式，系統(tǒng)的軟件設(shè)計采用基于VisualC++6．0的軟件設(shè)計模式。關(guān)鍵詞：GT-800運動控制器；貼片機；運動控制；機器視覺
標(biāo)簽： 800 GT 貼片機 控制系統(tǒng)
上傳時間： 2013-10-18
上傳用戶：asdkin
12864液晶時鐘顯示程序 LCD 地址變量 ;**************變量的定義***************** RS BIT P2.0 ;LCD數(shù)據(jù)/命令選擇端(H/L) RW BIT P2.1 ;LCD讀/寫選擇端(H/L) EP BIT P2.2 ;LCD使能控制 PSB EQU P2.3 RST EQU P2.5 PRE BIT P1.4 ;調(diào)整鍵(K1) ADJ BIT P1.5 ;調(diào)整鍵(K2) COMDAT EQU P0 LED EQU P0.3 YEAR DATA 18H ;年,月,日變量 MONTH DATA 19H DATE DATA 1AH WEEK DATA 1BH HOUR DATA 1CH ;時,分,秒,百分之一秒變量 MIN DATA 1DH SEC DATA 1EH SEC100 DATA 1FH STATE DATA 23H LEAP BIT STATE.1 ;是否閏年標(biāo)志1--閏年，0--平年 KEY_S DATA 24H ;當(dāng)前掃描鍵值 KEY_V DATA 25H ;上次掃描鍵值 DIS_BUF_U0 DATA 26H ;LCD第一排顯示緩沖區(qū) DIS_BUF_U1 DATA 27H DIS_BUF_U2 DATA 28H DIS_BUF_U3 DATA 29H DIS_BUF_U4 DATA 2AH DIS_BUF_U5 DATA 2BH DIS_BUF_U6 DATA 2CH DIS_BUF_U7 DATA 2DH DIS_BUF_U8 DATA 2EH DIS_BUF_U9 DATA 2FH DIS_BUF_U10 DATA 30H DIS_BUF_U11 DATA 31H DIS_BUF_U12 DATA 32H DIS_BUF_U13 DATA 33H DIS_BUF_U14 DATA 34H DIS_BUF_U15 DATA 35H DIS_BUF_L0 DATA 36H ;LCD第三排顯示緩沖區(qū) DIS_BUF_L1 DATA 37H DIS_BUF_L2 DATA 38H DIS_BUF_L3 DATA 39H DIS_BUF_L4 DATA 3AH DIS_BUF_L5 DATA 3BH DIS_BUF_L6 DATA 3CH DIS_BUF_L7 DATA 3DH DIS_BUF_L8 DATA 3EH DIS_BUF_L9 DATA 3FH DIS_BUF_L10 DATA 40H DIS_BUF_L11 DATA 41H DIS_BUF_L12 DATA 42H DIS_BUF_L13 DATA 43H DIS_BUF_L14 DATA 44H DIS_BUF_L15 DATA 45H FLAG DATA 46H ;1-年，2-月，3-日，4-時，5-分，6-秒，7-退出調(diào)整。 DIS_H DATA 47H DIS_M DATA 48H DIS_S DATA 49H
上傳時間： 2013-11-09
上傳用戶：xingisme
通過以太網(wǎng)遠(yuǎn)程配置Nios II 處理器 應(yīng)用筆記 Firmware in embedded hardware systems is frequently updated over the Ethernet. For embedded systems that comprise a discrete microprocessor and the devices it controls, the firmware is the software image run by the microprocessor. When the embedded system includes an FPGA, firmware updates include updates of the hardware image on the FPGA. If the FPGA includes a Nios® II soft processor, you can upgrade both the Nios II processor—as part of the FPGA image—and the software that the Nios II processor runs, in a single remote configuration session.
標(biāo)簽： Nios 遠(yuǎn)程 處理器 應(yīng)用筆記
上傳時間： 2013-11-22
上傳用戶：chaisz
面向Eclips的Nios II軟件構(gòu)建工具手冊 The Nios® II Software Build Tools (SBT) for Eclipse™ is a set of plugins based on the Eclipse™ framework and the Eclipse C/C++ development toolkit (CDT) plugins. The Nios II SBT for Eclipse provides a consistent development platform that works for all Nios II embedded processor systems. You can accomplish all Nios II software development tasks within Eclipse, including creating, editing, building, running, debugging, and profiling programs.
上傳時間： 2013-11-02
上傳用戶：瓦力瓦力hong
使用Nios II緊耦合存儲器教程 Chapter 1. Using Tightly Coupled Memory with the Nios II Processor Reasons for Using Tightly Coupled Memory . . . . . . . . . . . . . . . . . . . . . . . 1–1 Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Guidelines for Using Tightly Coupled Memory . . . .. . . . . . . . 1–2 Hardware Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Software Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 1–3 Locating Functions in Tightly Coupled Memory . . . . . . . . . . . . . 1–3 Tightly Coupled Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Dual Port Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 1–5 Building a Nios II System with Tightly Coupled Memory . . . . . . . . . . . 1–5
上傳時間： 2013-10-13
上傳用戶：黃婷婷思密達(dá)
Nios II 軟件開發(fā)人員手冊中的緩存和緊耦合存儲器部分 Nios® II embedded processor cores can contain instruction and data caches. This chapter discusses cache-related issues that you need to consider to guarantee that your program executes correctly on the Nios II processor. Fortunately, most software based on the Nios II hardware abstraction layer (HAL) works correctly without any special accommodations for caches. However, some software must manage the cache directly. For code that needs direct control over the cache, the Nios II architecture provides facilities to perform the following actions:
上傳時間： 2013-10-25
上傳用戶：蟲蟲蟲蟲蟲蟲
Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上傳時間： 2013-10-12
上傳用戶：kang1923
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