Wireless technology has been evolving at a breakneck speed. The total number of cell-phones in use (as of 2011) was over 6 billion for a 7 billion world population [1] constituting 87% of the world population. Additionally, with user convenience be- coming paramount, more and more functions are being implemented wirelessly.
標(biāo)簽： Front-Ends Cognitive Receiver Radio
上傳時(shí)間： 2020-05-26
上傳用戶：shancjb
This research work aims at eliminating the off-chip RF SAW filters from fre- quency division duplexed (FDD) receivers. In the first approach, a monolithic passive RF filter was constructed using on-chip capacitors and bondwire inductors. The bond- wire characteristics were studied in details and the effect of mutual inductive coupling between the bondwires on the filter performance was analyzed. Based on that, a bond- wire configuration was proposed to improve the frequency response of the filter. The filter was implemented in 0.18 μm CMOS process for WCDMA applications.
標(biāo)簽： Interference Mitigation Techniques
上傳時(shí)間： 2020-05-27
上傳用戶：shancjb
Modeling and simulation of nonlinear systems provide communication system designers with a tool to predict and verify overall system performance under nonlinearity and complex communication signals. Traditionally, RF system designers use deterministic signals (discrete tones), which can be implemented in circuit simulators, to predict the performance of their nonlinear circuits/systems. However, RF system designers are usually faced with the problem of predicting system performance when the input to the system is real-world communication signals which have a random nature.
標(biāo)簽： Nonlinear_Distortion_in_Wireless_ Systems
上傳時(shí)間： 2020-05-31
上傳用戶：shancjb
In this research, we have designed, developed implemented a wireless sensor networks based smart home for safe, sound and secured living environment for any inhabitant especially elderly living alone. We have explored a methodology for the development of efficient electronic real time data processing system to recognize the behaviour of an elderly person. The ability to determine the wellness of an elderly person living alone in their own home using a robust, flexible and data driven artificially intelligent system has been investigated. A framework integrating temporal and spatial contextual information for determining the wellness of an elderly person has been modelled. A novel behaviour detection process based on the observed sensor data in performing essential daily activities has been designed and developed.
上傳時(shí)間： 2020-06-06
上傳用戶：shancjb
In this chapter we give a quick overview of control theory, explaining why integral feedback control works, describing PID controllers, and summariz- ing some of the currently available techniques for PID controller design. This background will serve to motivate our results on PID control, pre- sented in the subsequent chapters.
標(biāo)簽： Controllers Time-Delay Systems PID for
上傳時(shí)間： 2020-06-10
上傳用戶：shancjb
這是我在做大學(xué)教授期間推薦給我學(xué)生的一本書，非常好，適合入門學(xué)習(xí)?！秔ython深度學(xué)習(xí)》由Keras之父、現(xiàn)任Google人工智能研究員的弗朗索瓦?肖萊（Franc?ois Chollet）執(zhí)筆，詳盡介紹了用Python和Keras進(jìn)行深度學(xué)習(xí)的探索實(shí)踐，包括計(jì)算機(jī)視覺、自然語(yǔ)言處理、產(chǎn)生式模型等應(yīng)用。書中包含30多個(gè)代碼示例，步驟講解詳細(xì)透徹。作者在github公布了代碼，代碼幾乎囊括了本書所有知識(shí)點(diǎn)。在學(xué)習(xí)完本書后，讀者將具備搭建自己的深度學(xué)習(xí)環(huán)境、建立圖像識(shí)別模型、生成圖像和文字等能力。但是有一個(gè)小小的遺憾：代碼的解釋和注釋是全英文的，即使英文水平較好的朋友看起來也很吃力。本人認(rèn)為，這本書和代碼是初學(xué)者入門深度學(xué)習(xí)及Keras最好的工具。作者在github公布了代碼，本人參照書本，對(duì)全部代碼做了中文解釋和注釋，并下載了代碼所需要的一些數(shù)據(jù)集（尤其是“貓狗大戰(zhàn)”數(shù)據(jù)集），并對(duì)其中一些圖像進(jìn)行了本地化，代碼全部測(cè)試通過。（請(qǐng)按照文件順序運(yùn)行，代碼前后有部分關(guān)聯(lián)）。以下代碼包含了全書約80%左右的知識(shí)點(diǎn)，代碼目錄：2.1: A first look at a neural network（ 初識(shí)神經(jīng)網(wǎng)絡(luò)）3.5: Classifying movie reviews（電影評(píng)論分類：二分類問題）3.6: Classifying newswires（新聞分類：多分類問題 ）3.7: Predicting house prices（預(yù)測(cè)房?jī)r(jià)：回歸問題）4.4: Underfitting and overfitting（ 過擬合與欠擬合）5.1: Introduction to convnets（卷積神經(jīng)網(wǎng)絡(luò)簡(jiǎn)介）5.2: Using convnets with small datasets（在小型數(shù)據(jù)集上從頭開始訓(xùn)練一個(gè)卷積網(wǎng)絡(luò)）5.3: Using a pre-trained convnet（使用預(yù)訓(xùn)練的卷積神經(jīng)網(wǎng)絡(luò)）5.4: Visualizing what convnets learn（卷積神經(jīng)網(wǎng)絡(luò)的可視化）
標(biāo)簽： python 深度學(xué)習(xí)
上傳時(shí)間： 2022-01-30
上傳用戶：
STM32L053C8T6數(shù)據(jù)手冊(cè)Features ? Ultra-low-power platform – 1.65 V to 3.6 V power supply – -40 to 125 °C temperature range – 0.27 μA Standby mode (2 wakeup pins) – 0.4 μA Stop mode (16 wakeup lines) – 0.8 μA Stop mode + RTC + 8 KB RAM retention – 139 μA/MHz Run mode at 32 MHz – 3.5 μs wakeup time (from RAM) – 5 μs wakeup time (from Flash) ? Core: ARM? 32-bit Cortex?-M0+ with MPU – From 32 kHz up to 32 MHz max. – 0.95 DMIPS/MHz ? Reset and supply management – Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds – Ultralow power POR/PDR – Programmable voltage detector (PVD) ? Clock sources – 1 to 25 MHz crystal oscillator – 32 kHz oscillator for RTC with calibration – High speed internal 16 MHz factory-trimmed RC (+/- 1%) – Internal low-power 37 kHz RC – Internal multispeed low-power 65 kHz to 4.2 MHz RC – PLL for CPU clock ? Pre-programmed bootloader – USART, SPI supported ? Development support – Serial wire debug supported ? Up to 51 fast I/Os (45 I/Os 5V tolerant) ? Memories – Up to 64 KB Flash with ECC – 8KB RAM – 2 KB of data EEPROM with ECC – 20-byte backup register
標(biāo)簽： stm32l053c8t6
上傳時(shí)間： 2022-02-06
上傳用戶：
數(shù)字示波器功能強(qiáng)大,使用方便,但是價(jià)格相對(duì)昂貴。本文以Ti的MSP430F5529為主控器,以Altera公司的EP2C5T144C8 FPGA器件為邏輯控制部件設(shè)計(jì)數(shù)字示波器。模擬信號(hào)經(jīng)程控放大、整形電路后形成方波信號(hào)送至FPGA測(cè)頻,根據(jù)頻率值選擇采用片上及片外高速AD分段采樣。FPGA控制片外AD采樣并將數(shù)據(jù)輸入到FIFO模塊中緩存,由單片機(jī)進(jìn)行頻譜分析。測(cè)試表明:簡(jiǎn)易示波器可以實(shí)現(xiàn)自動(dòng)選檔、多采樣率采樣、高精度測(cè)頻及頻譜分析等功能。Digital oscilloscope is powerful and easy to use, but also expensive. The research group designed a low-cost digital oscilloscope, the chip of MSP430F5529 of TI is chosen as the main controller and the device of EP2C5T144C8 of Altera company is used as the logic control unit. Analog signal enter the programmable amplifier circuit, shaping circuit and other pre-processing circuit. The shaped rectangular wave signal is sent to FPGA for measure the frequency. According to the frequency value to select AD on-chip or off-chip high-speed AD for sampling. FPGA controls the off-chip AD sampling and buffers AD data by FIFO module. The single chip microcomputer receives the data, and do FFT for spectrum analysis. The test shows that the simple oscilloscope can realize automatic gain selection, sampling at different sampling rates, high precision frequency measurement and spectrum analysis.
標(biāo)簽： msp430 單片機(jī) fpga 數(shù)字示波器
上傳時(shí)間： 2022-03-27
上傳用戶：
實(shí)驗(yàn)教學(xué)一直是工科教學(xué)中不可或缺的組成部分,對(duì)培養(yǎng)學(xué)生的動(dòng)手能力,獨(dú)立思考能力,創(chuàng)新思維與發(fā)散思維具有重要的作用。針對(duì)目前電路教學(xué)實(shí)驗(yàn)中電路仿真實(shí)驗(yàn)與實(shí)物電路實(shí)驗(yàn)各自獨(dú)立,無法統(tǒng)一問題,提出將仿真電路實(shí)驗(yàn)與實(shí)物電路實(shí)驗(yàn)有機(jī)的結(jié)合同步操作,并使用Web發(fā)布實(shí)現(xiàn)遠(yuǎn)程實(shí)驗(yàn)操作。采用Multisim作為電路實(shí)驗(yàn)仿真平臺(tái),NI Eiviss II作為實(shí)物電路實(shí)驗(yàn)硬件平臺(tái),運(yùn)用LabVIEW整合Multisim電路仿真實(shí)驗(yàn)與實(shí)物電路實(shí)驗(yàn),實(shí)現(xiàn)仿真與實(shí)物實(shí)驗(yàn)有機(jī)結(jié)合,兩種實(shí)驗(yàn)可同步進(jìn)行。學(xué)生在仿真實(shí)驗(yàn)中先可探索實(shí)驗(yàn),然后做實(shí)物實(shí)驗(yàn)。同時(shí)運(yùn)用LabVIEW開發(fā)出實(shí)驗(yàn)過程人機(jī)交互操作接口界面,使用過程中效果良好。Experimental teaching has always been an indispensable part of engineering education.And it always plays an important role in cultivating students'practical ability,independent thinking ability,innovative thinking and divergent thinking.But simulation experiment and physical experiment cannot be unified in the circuit teaching experiment at present.In order to solve this problem,this paper proposes to combine organically the simulation circuit experiment with physical circuit experiment,and synchronously operate them.This paper uses the WEB publishing to achieve remote experimental operation.Multisim is used as the circuit simulation platform,and NI Eiviss II is used as the physical circuit hardware platform.Multisim circuit simulation experiment and physical circuit experiment are implemented by LabVIEW to realize the combination of simulation experiment and physical experiment.Students do explore experiments in simulation experiment firstly,and then do physical experiment.And this paper uses LabVIEW to develop the experimental man-machine interface.
上傳時(shí)間： 2022-04-05
上傳用戶：
為了提高超高頻RFID系統(tǒng)中閱讀器在低信噪比的情況下仍具有較高的識(shí)別能力,提出一種基于FPGA系統(tǒng)結(jié)合軟件無線電方法實(shí)現(xiàn)超高頻RFID射頻前端電路方案。超高頻射頻識(shí)別系統(tǒng)必須符合EPC Class 1generation 2標(biāo)準(zhǔn),所設(shè)計(jì)的電路系統(tǒng)以Xilinx公司的XC6SLX16-2CSG324FPGA芯片為硬件基礎(chǔ),將數(shù)字基帶調(diào)制解調(diào)和中頻濾波電路在FPGA系統(tǒng)中設(shè)計(jì)實(shí)現(xiàn),重點(diǎn)闡述了射頻前端電路的設(shè)計(jì)結(jié)構(gòu)、AD/DA轉(zhuǎn)換電路,以及數(shù)字濾波器的設(shè)計(jì)。實(shí)驗(yàn)結(jié)果表明,所設(shè)計(jì)的超高頻RFID閱讀器簡(jiǎn)化了前端電路系統(tǒng)結(jié)構(gòu),提升了穩(wěn)定性,增強(qiáng)了抗干擾能力。該電路系統(tǒng)在信噪比較低的情況下,能夠較好地實(shí)現(xiàn)915MHz頻率的射頻接收和發(fā)送。In order to improve the reader UHF RFID system still has a higher ability to identify,in the case of low signal-to-noise ratio.The UHF RFID systems must comply with EPC Class 1 generation 2 standard.In this paper,the design of the circuit system based on Xilinx＇s XC6SLX16-2CSG324 FPGA chip,and presents UHF RFID RF front-end circuit with software radio based on FPGA system.Digital baseband modem and IF filter circuit is designed and implemented in the FPGA system,and focused on designing the structure of the RF front-end circuit,AD/DA conversion circuits,and digital filter.Experimental results show that the UHF RFID reader de...
標(biāo)簽： 915mhz 超高頻 rfid 閱讀 射頻 前端 電路 設(shè)計(jì)
上傳時(shí)間： 2022-04-17
上傳用戶：shjgzh
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