The pCI Local bus concept was developed to break
the PC data I/O bottleneck and clearly opens the door
to increasing system speed and expansion capabilities.
The pCI Local bus moves high speed peripherals
from the I/O bus and places them closer to the system’s
processor bus, providing faster data transfers
between the processor and peripherals. The pCI Local
bus also addresses the industry’s need for a bus standard
which is not directly dependent on the speed,
size and type of system processor. It represents the
first microprocessor independent bus offering performance
more than adequate for the most demanding
applications such as full-motion video.
The pCI Local bus concept was developed to break
the PC data I/O bottleneck and clearly opens the door
to increasing system speed and expansion capabilities.
The pCI Local bus moves high speed peripherals
from the I/O bus and places them closer to the system’s
processor bus, providing faster data transfers
between the processor and peripherals. The pCI Local
bus also addresses the industry’s need for a bus standard
which is not directly dependent on the speed,
size and type of system processor. It represents the
first microprocessor independent bus offering performance
more than adequate for the most demanding
applications such as full-motion video.
Hardware reference
The pCI Local bus concept was developed to break
the PC data I/O bottleneck and clearly opens the door
to increasing system speed and expansion capabilities.
The pCI Local bus moves high speed peripherals
from the I/O bus and places them closer to the system’s
processor bus, providing faster data transfers
between the processor and peripherals. The pCI Local
bus also addresses the industry’s need for a bus standard
which is not directly dependent on the speed,
size and type of system processor. It represents the
first microprocessor independent bus offering performance
more than adequate for the most demanding
applications such as full-motion video.
User Manual
pCI設計指南The Xilinx LogiCORE pCI interface is a fully verified, pre-implemented
pCI Bus interface. This interface is available in 32-bit and 64-
bit versions, with support for multiple Xilinx FPGA device families. It
is designed to support both Verilog-HDL and VHDL. The design
examples in this book are provided in Verilog.
