Multioutput monolithic regulators are easy to use and fi tinto spaces where multichip solutions cannot. Nevertheless,the popularity of multioutput regulators is temperedby a lack of options for input voltages above 30V andsupport of high output currents. The LT3692A fi lls thisgap with a dual monolithic regulator that operates frominputs up to 36V. It also includes a number of channeloptimization features that allow the LT3692A’s per-channelperformance to rival that of multichip solutions.
標(biāo)簽： 492 DN 降壓 溫度監(jiān)控
上傳時間： 2014-01-03
上傳用戶：Huge_Brother
§1、安裝： SPB15.2 CD1～3，安裝1、2，第3為庫，不安裝 License安裝： 設(shè)置環(huán)境變量lm_license_file D:\Cadence\license.dat 修改license中SERVER yyh ANY 5280為SERVER zeng ANY 5280 §2、用Design Entry CIS(Capture)設(shè)計(jì)原理圖 進(jìn)入Design Entry CIS Studio 設(shè)置操作環(huán)境\Options\Preferencses: 顏色：colors/Print 格子：Grid Display 雜項(xiàng)：Miscellaneous .........常取默認(rèn)值
上傳時間： 2013-11-13
上傳用戶：wangchong
西門子PLC S7-200編程軟件最新版本(2012.3) STEP7 MicroWIN_V4 SP9 完整版, 全面支持Windows7。安裝完后，打開軟件，初次為英文版，點(diǎn)擊tools（左上角自左-右第6個）然后選擇最下面的options（自上而下第15個）單擊，出現(xiàn)又一個畫面，在左邊選擇第一個選項(xiàng)General，就出現(xiàn)了語言選項(xiàng)，選擇最下面的那個（Chinese）也就是中文。然后點(diǎn)擊OK按鈕，然后一路回車下去，直到軟件關(guān)閉，再打開時就是中文的啦！
上傳時間： 2013-11-19
上傳用戶：mikesering
Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determine. Programmable logic devices can be configured in almost an infinitenumber of ways. The same design may fit when you use certain implementation switches, andfail to fit when using other switches. This application note attempts to clarify the CPLD softwareimplementation (CPLDFit) options, as well as discuss implementation tips in CoolRunnerTM-IIdesigns in order to maximize CPLD utilization.
上傳時間： 2014-01-11
上傳用戶：a471778
This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horizontal resolution, and implementation options. The rank to be selected can bemodified dynamically, and the actual horizontal resolution is picked up automatically from theinput synchronization signals. The design has a fully synchronous interface through the ce, clk,and rst ports.
上傳時間： 2013-12-14
上傳用戶：逗逗666
XAPP520將符合2.5V和3.3V I/O標(biāo)準(zhǔn)的7系列FPGA高性能I/O Bank進(jìn)行連接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上傳時間： 2013-11-06
上傳用戶：wentianyou
歡迎使用 PowerPCB 教程。本教程描述了 PADS-PowerPCB 的絕大部分功能和特點(diǎn)，以及使用的各個過程，這些功能包括： · 基本操作 · 建立元件(Component) · 建立板子邊框線(Board outline) · 輸入網(wǎng)表(Netlist) · 設(shè)置設(shè)計(jì)規(guī)則(Design Rule) · 元件(Part)的布局(Placement) · 手工和交互的布線 · SPECCTRA全自動布線器(Route Engine) · 覆銅(Copper Pour) · 建立分隔/混合平面層(Split/mixed Plane) · Microsoft的目標(biāo)連接與嵌入(OLE)(Object Linking Embedding) · 可選擇的裝配選件(Assembly options) · 設(shè)計(jì)規(guī)則檢查(Design Rule Check) · 反向標(biāo)注(Back Annotation) · 繪圖輸出(Plot Output) 使用本教程后，你可以學(xué)到印制電路板設(shè)計(jì)和制造的許多基本知識。
上傳時間： 2013-10-08
上傳用戶：x18010875091
15.2 已經(jīng)加入了有關(guān)貫孔及銲點(diǎn)的Z軸延遲計(jì)算功能. 先開啟 Setup - Constraints - Electrical constraint sets 下的 DRC 選項(xiàng). 點(diǎn)選 Electrical Constraints dialog box 下 Options 頁面 勾選 Z-Axis delay欄.
上傳時間： 2013-11-12
上傳用戶：Late_Li
§1、安裝： SPB15.2 CD1～3，安裝1、2，第3為庫，不安裝 License安裝： 設(shè)置環(huán)境變量lm_license_file D:\Cadence\license.dat 修改license中SERVER yyh ANY 5280為SERVER zeng ANY 5280 §2、用Design Entry CIS(Capture)設(shè)計(jì)原理圖 進(jìn)入Design Entry CIS Studio 設(shè)置操作環(huán)境\Options\Preferencses: 顏色：colors/Print 格子：Grid Display 雜項(xiàng)：Miscellaneous .........常取默認(rèn)值
上傳時間： 2014-01-25
上傳用戶：wangcehnglin
Debug.x：封裝SEH 作用：在程序發(fā)生未處理的異常時，利用SEH獲得異常時刻的信息，并將信息顯示或存儲到文件。 相關(guān)：pe文件操作 Stack操作
上傳時間： 2015-01-23
上傳用戶：lili123
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