一、變壓器Np、Ns、Lp的計算二、如果要計算氣隙長度Lg三、開關(guān)管Vce、Ic的計算（非連續(xù)）五.輸出整流二極管Id、Vd的計算Flyback輸出濾波電容設(shè)計流過輸出電容C的紋波電流Ic=I2- Io 其中：I2為次級線圈電流 Ic的有效值可由下式計算：Icrms=[Ton/3T(I2p^2-I2pIo+Io^2 )+(Toff/T)* Io^2]^1/2 其中I2p=2io/(1- δmax) 此為輸入電壓最低、輸出功率最大時狀態(tài)。
上傳時間： 2013-11-22
上傳用戶：aesuser
QSP-12是一款性/價比極高的直接使用USB通訊協(xié)議而開發(fā)的三星單片機專用編程器。不同于傳統(tǒng)采用USB轉(zhuǎn)RS232的編程器，直接使用USB通訊協(xié)議的QSP-12更快更可靠！配合精心優(yōu)化設(shè)計的PC客戶端編程（燒錄）軟件，實現(xiàn)了業(yè)界最高的編程性能。自動燒錄S3F9454（包含擦除/編程/校驗/寫Smart option/Read protect/LDC protect/Hard Lock）只須0.7秒，代碼越小，燒錄越快；代碼越大，優(yōu)勢越明顯！ 編程器采用小巧而堅實的烤漆鐵質(zhì)外殼設(shè)計，具有極高的耐用性和抗電磁干擾能力，配備防止反插的RJ-11專業(yè)在線編程接口，確保您在使用過程中沒機會出錯。QSP-12快速可靠的編程（燒錄）能力，無論是您在產(chǎn)品開發(fā)、量產(chǎn)，還是在產(chǎn)品的現(xiàn)場升級階段，它都能給您帶來前所未有高效、可靠的編程體驗！在現(xiàn)今人力成本日益高漲的時代，為您贏得更多優(yōu)勢！ QSP-12特點： 直接使用USB通訊，更快、更可靠 無需用戶設(shè)定編程電壓，更安全、易用 業(yè)界最高的編程性能，節(jié)省人力成本 支持脫機燒錄 支持在線編程（ISP） 外形小巧，方便產(chǎn)品現(xiàn)場升級 堅實的烤漆鐵質(zhì)外殼，更美觀耐用、抗電磁干擾能力強 低功耗（<0.5W），綠色環(huán)保
上傳時間： 2013-11-19
上傳用戶：uuuuuuu
winCE msdn講座 XP Embedded Now and the future Windows XP Embedded Developmentand Deployment Model OverviewWindows XP Embedded Component ModelWindows XP Embedded Studio Tools Microsoft WindowsXP Embedded Product Highlights Componentized version of Windows XP Professional~ 12,000 components and updates as of Service Pack 2Flexible localizationSame binaries and API as Windows XP ProfessionalHotfixes and service packsEmbedded Enabling FeaturesRuns on standard PC hardwareSupports boot on hard drives, compact flash, DiskOnChipand read-only mediaSupport for remote install and remote bootHeadless device and remote management supportIntegration with Microsoft management tools
上傳時間： 2013-10-31
上傳用戶：jrsoft
針對傳統(tǒng)集成電路（ASIC）功能固定、升級困難等缺點，利用FPGA實現(xiàn)了擴頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實現(xiàn)NCO模塊，在下變頻模塊調(diào)用了硬核乘法器并引入CIC濾波器進行低通濾波，給出了DQPSK解調(diào)的原理和實現(xiàn)方法，推導(dǎo)出一種簡便的引入?仔/4固定相移的實現(xiàn)方法。采用模塊化的設(shè)計方法使用VHDL語言編寫出源程序，在Virtex-II Pro 開發(fā)板上成功實現(xiàn)了整個系統(tǒng)。測試結(jié)果表明該系統(tǒng)正確實現(xiàn)了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
上傳時間： 2013-11-06
上傳用戶：liu123
文中詳細地介紹了正交投影子空間跟蹤算法（OPAST），它是一種基于最優(yōu)化問題的方法，保證了每次迭代時權(quán)向量的正交性，并具有和PAST算法一樣的線性復(fù)雜度，以及與自然冪法（NP）一樣的全局收斂性。然而將其應(yīng)用于盲多用戶檢測時，在迭代一定次數(shù)后，會出現(xiàn)誤碼率突然增大現(xiàn)象，這就導(dǎo)致了算法性能的下降，為了解決這一問題，文中提出一種方法，并通過仿真結(jié)果，證明它是行之有效的。
標簽： OPAST 算法 多用戶檢測 中的應(yīng)用
上傳時間： 2014-11-11
上傳用戶：xaijhqx
There is no doubt that remote controls are extremely popular and it has become very hard to imagine a world without them. They are used to control all manner of house appliances like the TV set, the stereo, the VCR, and the satellite receiver.
上傳時間： 2013-11-13
上傳用戶：頂?shù)弥?/p>
針對傳統(tǒng)集成電路（ASIC）功能固定、升級困難等缺點，利用FPGA實現(xiàn)了擴頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實現(xiàn)NCO模塊，在下變頻模塊調(diào)用了硬核乘法器并引入CIC濾波器進行低通濾波，給出了DQPSK解調(diào)的原理和實現(xiàn)方法，推導(dǎo)出一種簡便的引入?仔/4固定相移的實現(xiàn)方法。采用模塊化的設(shè)計方法使用VHDL語言編寫出源程序，在Virtex-II Pro 開發(fā)板上成功實現(xiàn)了整個系統(tǒng)。測試結(jié)果表明該系統(tǒng)正確實現(xiàn)了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
上傳時間： 2013-11-19
上傳用戶：neu_liyan
本文利用Verilog HDL 語言自頂向下的設(shè)計方法設(shè)計多功能數(shù)字鐘，突出了其作為硬件描述語言的良好的可讀性、可移植性和易理解等優(yōu)點，并通過Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過下載到FPGA 芯片后，可應(yīng)用于實際的數(shù)字鐘顯示中。 關(guān)鍵詞：Verilog HDL；硬件描述語言；FPGA Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip. Keywords: Verilog HDL；hardware description language；FPGA
上傳時間： 2013-11-10
上傳用戶：hz07104032
tty驅(qū)動 * This driver shows how to create a minimal tty driver. It does not rely on * any backing hardware, but creates a timer that emulates data being received * from some kind of hardware.
標簽： driver tty backing minimal
上傳時間： 2013-12-04
上傳用戶：金宜
This companion disc contains the source code for the sample programs presented in INSIDE VISUAL C++ 5.0, as well as pre- compiled copies of the programs. To copy all of the sample code onto your hard disk, run the SETUP.EXE program and follow the instructions that appear on the screen. The sample code requires about 10 MB of hard disk space.
標簽： companion the presented contains
上傳時間： 2015-05-09
上傳用戶：mhp0114
蟲蟲下載站版權(quán)所有 京ICP備2021023401號-1
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